Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838452
E. Casu, W. Vitale, N. Oliva, T. Rosca, A. Biswas, C. Alper, A. Krammer, G. V. Luong, Q. Zhao, S. Mantl, A. Schuler, A. Seabaugh, A. Ionescu
In this paper we report the first hybrid Phase-Change — Tunnel FET (PC-TFET) device configurations for achieving a deep sub-thermionic steep subthreshold swing at room temperature and subthreshold power savings. The proposed hybrid device feedbacks the steep transition of Metal-Insulator transition in a VO2 structure into Gate or Source configurations of strained silicon nanowire Tunnel FETs, to achieve a switching with lon/Ioff better that 5.5×106 and with a subthreshold swing of 4.0 mV/dec at 25 °C. We demonstrate that the principle of PC-TFET switching relates to an internal amplification resulting in a sub-unity body factor, m, which is reduced to values below 0.1 for a current range larger than 2–3 decades. We report a full experimental digital and analog benchmarking of the new device and compare it with Tunnel FETs and CMOS. Remarkably, the PC-TFET can achieve analog figures of merit like gm/Id breaking the 40 V−1 limit of MOSFETs. We demonstrate and report the first buffered oscillator cell for neuromorphic computing exploiting the gate configuration of PC-TFET.
{"title":"Hybrid phase-change — Tunnel FET (PC-TFET) switch with subthreshold swing < 10mV/decade and sub-0.1 body factor: Digital and analog benchmarking","authors":"E. Casu, W. Vitale, N. Oliva, T. Rosca, A. Biswas, C. Alper, A. Krammer, G. V. Luong, Q. Zhao, S. Mantl, A. Schuler, A. Seabaugh, A. Ionescu","doi":"10.1109/IEDM.2016.7838452","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838452","url":null,"abstract":"In this paper we report the first hybrid Phase-Change — Tunnel FET (PC-TFET) device configurations for achieving a deep sub-thermionic steep subthreshold swing at room temperature and subthreshold power savings. The proposed hybrid device feedbacks the steep transition of Metal-Insulator transition in a VO2 structure into Gate or Source configurations of strained silicon nanowire Tunnel FETs, to achieve a switching with lon/Ioff better that 5.5×106 and with a subthreshold swing of 4.0 mV/dec at 25 °C. We demonstrate that the principle of PC-TFET switching relates to an internal amplification resulting in a sub-unity body factor, m, which is reduced to values below 0.1 for a current range larger than 2–3 decades. We report a full experimental digital and analog benchmarking of the new device and compare it with Tunnel FETs and CMOS. Remarkably, the PC-TFET can achieve analog figures of merit like gm/Id breaking the 40 V−1 limit of MOSFETs. We demonstrate and report the first buffered oscillator cell for neuromorphic computing exploiting the gate configuration of PC-TFET.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132690707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838480
J.H. Han, M. Takenaka, S. Takagi
We have demonstrated an optical modulator with an InGaAsP/Si hybrid MOS-based phase shifter on Si photonics platform by using direct wafer bonding. Since the electron-induced refractive index change in InGaAsP is much greater than Si, electron accumulation at the InGaAsP MOS interface enables an extremely high modulation efficiency. In conjunction with the void-free direct wafer bonding with ALD Al2O3 bonding interface, we have achieved the superior InGaAsP/Al2O3/Si hybrid MOS interface. Thus, we have successfully fabricated the InGaAsP/Si hybrid MOS optical modulator, exhibiting a modulation efficiency VπL of 0.047 Vcm, approximately 5 times better than that of Si-based MOS optical modulators reported so far even with a similar EOT of 5 nm. Thus, the heterogeneous integration of InGaAsP on Si is effective for significantly improving performance of MOS optical modulators through breaking the inherent trade-off between the EOT scaling and modulation bandwidth.
{"title":"Extremely high modulation efficiency IU-V/Si hybrid MOS optical modulator fabricated by direct wafer bonding","authors":"J.H. Han, M. Takenaka, S. Takagi","doi":"10.1109/IEDM.2016.7838480","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838480","url":null,"abstract":"We have demonstrated an optical modulator with an InGaAsP/Si hybrid MOS-based phase shifter on Si photonics platform by using direct wafer bonding. Since the electron-induced refractive index change in InGaAsP is much greater than Si, electron accumulation at the InGaAsP MOS interface enables an extremely high modulation efficiency. In conjunction with the void-free direct wafer bonding with ALD Al2O3 bonding interface, we have achieved the superior InGaAsP/Al2O3/Si hybrid MOS interface. Thus, we have successfully fabricated the InGaAsP/Si hybrid MOS optical modulator, exhibiting a modulation efficiency VπL of 0.047 Vcm, approximately 5 times better than that of Si-based MOS optical modulators reported so far even with a similar EOT of 5 nm. Thus, the heterogeneous integration of InGaAsP on Si is effective for significantly improving performance of MOS optical modulators through breaking the inherent trade-off between the EOT scaling and modulation bandwidth.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"431 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132724857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838481
J. Veres, R. Bringans, E. Chow, J. P. Lu, P. Mei, S. Ready, D. Schwartz, R. Street
Additive manufacturing and 3D printing are poised to reshape entire manufacturing value chains. To be truly disruptive, additive manufacturing has to move beyond shapes and colors. Novel printing technologies are beginning to emerge that enable conformal electronics and even printing with inks containing microchips. This in turn also creates new openings for the progress of electronics itself. Over the last 50 years silicon microelectronics advanced through shrinking device dimensions and packing more and more functionality into tiny spaces. Printing technologies open up exciting new ways of scaling electronics “Beyond Moore”, through the integration of micro and macro, creating new form factors, complex shapes, conformal devices and distributed systems. Printed, hybrid electronics systems will enable new classes of sensor systems, structural electronics and wearable devices, where the “system is the package”.
{"title":"Additive manufacturing for electronics “Beyond Moore”","authors":"J. Veres, R. Bringans, E. Chow, J. P. Lu, P. Mei, S. Ready, D. Schwartz, R. Street","doi":"10.1109/IEDM.2016.7838481","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838481","url":null,"abstract":"Additive manufacturing and 3D printing are poised to reshape entire manufacturing value chains. To be truly disruptive, additive manufacturing has to move beyond shapes and colors. Novel printing technologies are beginning to emerge that enable conformal electronics and even printing with inks containing microchips. This in turn also creates new openings for the progress of electronics itself. Over the last 50 years silicon microelectronics advanced through shrinking device dimensions and packing more and more functionality into tiny spaces. Printing technologies open up exciting new ways of scaling electronics “Beyond Moore”, through the integration of micro and macro, creating new form factors, complex shapes, conformal devices and distributed systems. Printed, hybrid electronics systems will enable new classes of sensor systems, structural electronics and wearable devices, where the “system is the package”.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"16 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129455778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838366
Zhe Zhang, Zexuan Zhang, Runsheng Wang, Xiaobo Jiang, Shaofeng Guo, Yangyuan Wang, Xingsheng Wang, B. Cheng, A. Asenov, Ru Huang
The concept of percolative channel is essential for understanding statistical variability and reliability in nanoscale transistors. In this paper, the quantitative factors of channel current percolation path (PP) are comprehensively studied in planar and FinFET devices for the first time, with statistical simulations and experimental characterizations. The properly-defined PP parameters are well quantified by the proposed new approach, and extracted from ‘atomistic’ device simulation. The experimental data of random telegraph noise (RTN) is used via the atomic PP model to characterize the underlying channel local current fluctuations and thus to benchmark the PP in reality. Experimental results of extracted PP parameters are consistent with those predicted from simulations, confirming the effectiveness of the proposed approach. The 3D PP in FinFET has different features compared with 2D PP in planar devices, and exhibits additional distortion along Fin-width direction. This work provides a unique framework for deep understanding of “random device physics” and thus is helpful for future nano-device design.
{"title":"New approach for understanding “random device physics” from channel percolation perspectives: Statistical simulations, key factors and experimental results","authors":"Zhe Zhang, Zexuan Zhang, Runsheng Wang, Xiaobo Jiang, Shaofeng Guo, Yangyuan Wang, Xingsheng Wang, B. Cheng, A. Asenov, Ru Huang","doi":"10.1109/IEDM.2016.7838366","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838366","url":null,"abstract":"The concept of percolative channel is essential for understanding statistical variability and reliability in nanoscale transistors. In this paper, the quantitative factors of channel current percolation path (PP) are comprehensively studied in planar and FinFET devices for the first time, with statistical simulations and experimental characterizations. The properly-defined PP parameters are well quantified by the proposed new approach, and extracted from ‘atomistic’ device simulation. The experimental data of random telegraph noise (RTN) is used via the atomic PP model to characterize the underlying channel local current fluctuations and thus to benchmark the PP in reality. Experimental results of extracted PP parameters are consistent with those predicted from simulations, confirming the effectiveness of the proposed approach. The 3D PP in FinFET has different features compared with 2D PP in planar devices, and exhibits additional distortion along Fin-width direction. This work provides a unique framework for deep understanding of “random device physics” and thus is helpful for future nano-device design.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132786731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838391
Junjie An, Masaki Namai, M. Tanabe, D. Okamoto, H. Yano, N. Iwamuro
A new p-channel vertical 4H-SiC MOSFET has been successfully fabricated for the first time. Its breakdown voltage is over −730 V and the short circuit capability is 15% higher than that of 4H-SiC n-channel MOSFET. This could be a superior power device applicable for high frequency complementary inverter.
{"title":"Experimental demonstration of −730V vertical SiC p-MOSFET with high short circuit withstand capability for complementary inverter applications","authors":"Junjie An, Masaki Namai, M. Tanabe, D. Okamoto, H. Yano, N. Iwamuro","doi":"10.1109/IEDM.2016.7838391","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838391","url":null,"abstract":"A new p-channel vertical 4H-SiC MOSFET has been successfully fabricated for the first time. Its breakdown voltage is over −730 V and the short circuit capability is 15% higher than that of 4H-SiC n-channel MOSFET. This could be a superior power device applicable for high frequency complementary inverter.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132495950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838426
S. Shin, S. H. Kim, S. Kim, H. Wu, P. Ye, M. Alam
Self-heating (SH) has emerged as an important performance, variability, and reliability concern for floating body transistors (FB-FET), namely, extremely-thin-silicon-on-insulator (ETSOI), SOI-FinFET, gate-all-round NW-FET (GAA-FETs), etc. The floating body topology offers electrostatic control, but restricts heat outflow: apparently an intrinsic trade-off. In this paper, we trace the trajectory of heat flow in a broad range of transistors to show that the trade-off is not fundamental, and self-heating can be suppressed by novel device designs that ease thermal bottlenecks. Towards this goal, we (i) characterize SH in various FB-FETs with different channel materials (Si, Ge, InGaAs) by submicron thermo-reflectance imaging; (ii) identify universal features and common thermal bottlenecks across various transistor technologies, (iii) offer novel, technology-aware device design to ease the bottlenecks and reduce self-heating, and (iv) experimentally demonstrate the effectiveness of these strategies in suppressing self-heating. We conclude that thermal aware transistor design can suppress self-heating without compromising performance and electrostatic control of the transistor.
{"title":"Substrate and layout engineering to suppress self-heating in floating body transistors","authors":"S. Shin, S. H. Kim, S. Kim, H. Wu, P. Ye, M. Alam","doi":"10.1109/IEDM.2016.7838426","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838426","url":null,"abstract":"Self-heating (SH) has emerged as an important performance, variability, and reliability concern for floating body transistors (FB-FET), namely, extremely-thin-silicon-on-insulator (ETSOI), SOI-FinFET, gate-all-round NW-FET (GAA-FETs), etc. The floating body topology offers electrostatic control, but restricts heat outflow: apparently an intrinsic trade-off. In this paper, we trace the trajectory of heat flow in a broad range of transistors to show that the trade-off is not fundamental, and self-heating can be suppressed by novel device designs that ease thermal bottlenecks. Towards this goal, we (i) characterize SH in various FB-FETs with different channel materials (Si, Ge, InGaAs) by submicron thermo-reflectance imaging; (ii) identify universal features and common thermal bottlenecks across various transistor technologies, (iii) offer novel, technology-aware device design to ease the bottlenecks and reduce self-heating, and (iv) experimentally demonstrate the effectiveness of these strategies in suppressing self-heating. We conclude that thermal aware transistor design can suppress self-heating without compromising performance and electrostatic control of the transistor.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130231736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838484
C. Ahn, D. L. Christensen, D. Heinz, V. Hong, E. Ng, Janna Rodriguez, Yushi Yang, G. O'brien, T. Kenny
There is significant interest in integration of multiple MEMS functionalities into a single compact device. Our group has developed a wafer-scale encapsulation process that provides an ultraclean, stable environment for operation of MEMS timing references, which has been commercialized by SiTime, Inc. In this paper, we discuss some of the issues associated with incorporation of inertial sensors into this encapsulation process, including design constraints, stiction, pressure, and other issues.
{"title":"Encapsulated inertial systems","authors":"C. Ahn, D. L. Christensen, D. Heinz, V. Hong, E. Ng, Janna Rodriguez, Yushi Yang, G. O'brien, T. Kenny","doi":"10.1109/IEDM.2016.7838484","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838484","url":null,"abstract":"There is significant interest in integration of multiple MEMS functionalities into a single compact device. Our group has developed a wafer-scale encapsulation process that provides an ultraclean, stable environment for operation of MEMS timing references, which has been commercialized by SiTime, Inc. In this paper, we discuss some of the issues associated with incorporation of inertial sensors into this encapsulation process, including design constraints, stiction, pressure, and other issues.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"173 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133312760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838439
G. Tsutsui, R. Bao, K. Lim, R. Robison, R. Vega, Jie Yang, Zuoguang Liu, Miaomiao Wang, O. Gluschenkov, C. Yeung, Koji Watanabe, S. Bentley, H. Niimi, Derrick Liu, Huimei Zhou, S. Siddiqui, Hoon Kim, R. Galatage, R. Venigalla, M. Raymond, P. Adusumilli, S. Mochizuki, T. Devarajan, Bruce Miao, Bei Liu, A. Greene, J. Shearer, P. Montanini, J. Strane, C. Prindle, E. Miller, J. Fronheiser, C. Niu, K. Chung, J. Kelly, H. Jagannathan, S. Kanakasabapathy, G. Karve, F. Lie, P. Oldiges, V. Narayanan, T. Hook, A. Knorr, D. Gupta, D. Guo, R. Divakaruni, H. Bu, M. Khare
Low Ge content SiGe-based CMOS FinFET is one of the promising technologies [1-2] offering solutions for both high performance and low power applications. In this paper, we established a competitive SiGe-based CMOS FinFET baseline and examined various elements for high performance offering. The performance elements in gate stack, channel doping, contact resistance, and junction have been explored to provide a cumulative 20% / 25% (n/pFET) performance enhancement. These elements provide a viable path towards performance enhancement for future technology nodes.
{"title":"Technology viable DC performance elements for Si/SiGe channel CMOS FinFTT","authors":"G. Tsutsui, R. Bao, K. Lim, R. Robison, R. Vega, Jie Yang, Zuoguang Liu, Miaomiao Wang, O. Gluschenkov, C. Yeung, Koji Watanabe, S. Bentley, H. Niimi, Derrick Liu, Huimei Zhou, S. Siddiqui, Hoon Kim, R. Galatage, R. Venigalla, M. Raymond, P. Adusumilli, S. Mochizuki, T. Devarajan, Bruce Miao, Bei Liu, A. Greene, J. Shearer, P. Montanini, J. Strane, C. Prindle, E. Miller, J. Fronheiser, C. Niu, K. Chung, J. Kelly, H. Jagannathan, S. Kanakasabapathy, G. Karve, F. Lie, P. Oldiges, V. Narayanan, T. Hook, A. Knorr, D. Gupta, D. Guo, R. Divakaruni, H. Bu, M. Khare","doi":"10.1109/IEDM.2016.7838439","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838439","url":null,"abstract":"Low Ge content SiGe-based CMOS FinFET is one of the promising technologies [1-2] offering solutions for both high performance and low power applications. In this paper, we established a competitive SiGe-based CMOS FinFET baseline and examined various elements for high performance offering. The performance elements in gate stack, channel doping, contact resistance, and junction have been explored to provide a cumulative 20% / 25% (n/pFET) performance enhancement. These elements provide a viable path towards performance enhancement for future technology nodes.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134286817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838430
Chieh-Pu Lo, Wei-Hao Chen, Zhibo Wang, Albert Lee, Kuo-Hsiang Hsu, Fang Su, Y. King, C. Lin, Yongpan Liu, Huazhong Yang, P. Khalili, Kang L. Wang, Meng-Fan Chang
Recent nonvolatile flip-flops (nvFFs) enable the parallel movement of data locally between flip-flops (FFs) and nonvolatile memory (NVM) devices for faster system power off/on operations. The wide distribution and long period in NVM-write times of previous two-NVM-based nvFFs result in excessive store energy (Es) and over-write induced reliability degradation for NVM-write operations. This work proposes an nvFF using a single NVM (1R) with self-write-termination (SWT), capable of reducing ES by 27+x and avoid over-write operations. In fabricated 65nm ReRAM nvProcessor testchips, the proposed SWT1R nvFFs achieved off/on operations with a 99% reduction in Es and 2.7ns SWT latency (TSWT). For the first time, an nvFF with single NVM device is presented.
{"title":"A ReRAM-based single-NVM nonvolatile flip-flop with reduced stress-time and write-power against wide distribution in write-time by using self-write-termination scheme for nonvolatile processors in IoT era","authors":"Chieh-Pu Lo, Wei-Hao Chen, Zhibo Wang, Albert Lee, Kuo-Hsiang Hsu, Fang Su, Y. King, C. Lin, Yongpan Liu, Huazhong Yang, P. Khalili, Kang L. Wang, Meng-Fan Chang","doi":"10.1109/IEDM.2016.7838430","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838430","url":null,"abstract":"Recent nonvolatile flip-flops (nvFFs) enable the parallel movement of data locally between flip-flops (FFs) and nonvolatile memory (NVM) devices for faster system power off/on operations. The wide distribution and long period in NVM-write times of previous two-NVM-based nvFFs result in excessive store energy (Es) and over-write induced reliability degradation for NVM-write operations. This work proposes an nvFF using a single NVM (1R) with self-write-termination (SWT), capable of reducing ES by 27+x and avoid over-write operations. In fabricated 65nm ReRAM nvProcessor testchips, the proposed SWT1R nvFFs achieved off/on operations with a 99% reduction in Es and 2.7ns SWT latency (TSWT). For the first time, an nvFF with single NVM device is presented.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116562765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838477
L. Xu, S. Shibayama, Kazutaka Izukashi, T. Nishimura, T. Yajima, S. Migita, A. Toriumi
This work discusses the general relationship for cation and anion doping effects on the HfO2 para-/ferroelectric transition, which will provide us a helpful instruction for precise HfO2 ferroelectricity design. In addition, ferroelectric N-doped HfO2 has been demonstrated as a gate dielectric film on an oxide semiconductor for ferroelectric field-effect transistors (FeFETs).
{"title":"General relationship for cation and anion doping effects on ferroelectric HfO2 formation","authors":"L. Xu, S. Shibayama, Kazutaka Izukashi, T. Nishimura, T. Yajima, S. Migita, A. Toriumi","doi":"10.1109/IEDM.2016.7838477","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838477","url":null,"abstract":"This work discusses the general relationship for cation and anion doping effects on the HfO2 para-/ferroelectric transition, which will provide us a helpful instruction for precise HfO2 ferroelectricity design. In addition, ferroelectric N-doped HfO2 has been demonstrated as a gate dielectric film on an oxide semiconductor for ferroelectric field-effect transistors (FeFETs).","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125779862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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