Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838494
H. Noguchi, K. Ikegami, K. Abe, S. Fujita, Y. Shiota, T. Nozaki, S. Yuasa, Yoshishige Suzuki
This paper presents voltage controlled MRAM (VCM) with novel fast read/write circuits for nonvolatile ultra-large last level cache. Further, write error rate has dramatically been reduced by thermal stability factor control using “continuous read-write-verify” scheme. Read error rate has also improved with “read-disturb-free non-destructive-self-reference read” with unipolar write of VCM.
{"title":"Novel voltage controlled MRAM (VCM) with fast read/write circuits for ultra large last level cache","authors":"H. Noguchi, K. Ikegami, K. Abe, S. Fujita, Y. Shiota, T. Nozaki, S. Yuasa, Yoshishige Suzuki","doi":"10.1109/IEDM.2016.7838494","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838494","url":null,"abstract":"This paper presents voltage controlled MRAM (VCM) with novel fast read/write circuits for nonvolatile ultra-large last level cache. Further, write error rate has dramatically been reduced by thermal stability factor control using “continuous read-write-verify” scheme. Read error rate has also improved with “read-disturb-free non-destructive-self-reference read” with unipolar write of VCM.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126098859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838500
J. Jing, Susan Wu, Xin Wu, P. Upadhyaya, Ade Bekele
For the first time, an optimized MOS varactor device design and a new physical based varactor model for advanced FinFET process is presented for high speed analog applications. The varactor is optimized in process and cell design to achieve high tuning range and low jitter for PLL design. A new physical BSIMCMG based varactor model is developed with RF components to fully describe the 3D device in FinFET technology for high frequency applications. The power dependent varactor CV characteristics and modeling for accurate VCO simulation is described. The new varactor device and model has been validated in 32.75 GB/s high speed transceiver design in 16nm FinFET technology.
{"title":"Novel MOS varactor device optimization and modeling for high-speed transceiver design in FinFET technology","authors":"J. Jing, Susan Wu, Xin Wu, P. Upadhyaya, Ade Bekele","doi":"10.1109/IEDM.2016.7838500","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838500","url":null,"abstract":"For the first time, an optimized MOS varactor device design and a new physical based varactor model for advanced FinFET process is presented for high speed analog applications. The varactor is optimized in process and cell design to achieve high tuning range and low jitter for PLL design. A new physical BSIMCMG based varactor model is developed with RF components to fully describe the 3D device in FinFET technology for high frequency applications. The power dependent varactor CV characteristics and modeling for accurate VCO simulation is described. The new varactor device and model has been validated in 32.75 GB/s high speed transceiver design in 16nm FinFET technology.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129746520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838333
Shien-Yang Wu, Lin Chih-Yung, M. Chiang, J. Liaw, J. Cheng, S. Yang, C. Tsai, P. Chen, T. Miyashita, Chang-Yun Chang, V. Chang, K. Pan, J. Chen, Y. Mor, K. Lai, C. Liang, Chen Hsin-Chi, S. Chang, Chia-Pin Lin, C. Hsieh, R. F. Tsui, C. Yao, C. C. Chen, R. Chen, C. Lee, Hau-Yu Lin, Chih-Sheng Chang, K. W. Chen, M. Tsai, Kuei-Shun Chen, Y. Ku, S. Jang
For the first time, a leading edge 7nm CMOS platform technology for mobile SoC applications is presented. This technology provides >3.3X routed gate density and 35%∼40% speed gain or >65% power reduction over our 16nm FinFET technology. A fully functional 256Mb SRAM test-chip with the smallest high density SRAM cell of 0.027um2 is demonstrated down to 0.5V. The 4th generation FinFET transistors are optimized with device mismatch reduction by 25%∼35% and multi-Vt device options to enable low power and high performance design requirements.
{"title":"A 7nm CMOS platform technology featuring 4th generation FinFET transistors with a 0.027um2 high density 6-T SRAM cell for mobile SoC applications","authors":"Shien-Yang Wu, Lin Chih-Yung, M. Chiang, J. Liaw, J. Cheng, S. Yang, C. Tsai, P. Chen, T. Miyashita, Chang-Yun Chang, V. Chang, K. Pan, J. Chen, Y. Mor, K. Lai, C. Liang, Chen Hsin-Chi, S. Chang, Chia-Pin Lin, C. Hsieh, R. F. Tsui, C. Yao, C. C. Chen, R. Chen, C. Lee, Hau-Yu Lin, Chih-Sheng Chang, K. W. Chen, M. Tsai, Kuei-Shun Chen, Y. Ku, S. Jang","doi":"10.1109/IEDM.2016.7838333","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838333","url":null,"abstract":"For the first time, a leading edge 7nm CMOS platform technology for mobile SoC applications is presented. This technology provides >3.3X routed gate density and 35%∼40% speed gain or >65% power reduction over our 16nm FinFET technology. A fully functional 256Mb SRAM test-chip with the smallest high density SRAM cell of 0.027um2 is demonstrated down to 0.5V. The 4th generation FinFET transistors are optimized with device mismatch reduction by 25%∼35% and multi-Vt device options to enable low power and high performance design requirements.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129012975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838495
H. Yoda, N. Shimomura, Y. Ohsawa, S. Shirotori, Y. Kato, T. Inokuchi, Y. Kamiguchi, B. Altansargai, Y. Saito, K. Koi, H. Sugiyama, S. Oikawa, M. Shimizu, M. Ishikawa, K. Ikegami, A. Kurobe
We propose a new spintronics-based memory employing the voltage-control-magnetic-anisotropy effect as a bit selecting principle and the spin-orbit-torque effect as a writing principle. We have fabricated the prototype structure, and successfully demonstrated the writing scheme specific to this memory architecture.
{"title":"Voltage-control spintronics memory (VoCSM) having potentials of ultra-low energy-consumption and high-density","authors":"H. Yoda, N. Shimomura, Y. Ohsawa, S. Shirotori, Y. Kato, T. Inokuchi, Y. Kamiguchi, B. Altansargai, Y. Saito, K. Koi, H. Sugiyama, S. Oikawa, M. Shimizu, M. Ishikawa, K. Ikegami, A. Kurobe","doi":"10.1109/IEDM.2016.7838495","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838495","url":null,"abstract":"We propose a new spintronics-based memory employing the voltage-control-magnetic-anisotropy effect as a bit selecting principle and the spin-orbit-torque effect as a writing principle. We have fabricated the prototype structure, and successfully demonstrated the writing scheme specific to this memory architecture.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124358315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838488
Chun-You Liu, Ming-Huang Li, H. Ranjith, Sheng-Shian Li
A 1 MHz 4 ppm temperature-stable micro-oven μOven) controlled monolithic CMOS-MEMS oscillator has been demonstrated in this work, exhibiting heating power in sub-mW across the 100°C temperature span. The proposed novel isothermal μOven platform consists of dual heaters, one of which stabilizes the resonator temperature while the other of which serves as built-in self-test (BIST) to mimic ambient temperature, and a resistive temperature detector (RTD) for local resonator temperature monitoring. By adapting the constant-resistance (CR) feedback temperature control scheme, the integrated 1 MHz CMOS-MEMS oscillator shows a maximum frequency inaccuracy of only 4 ppm during a fast temperature ramp across the 94°C testing span (i.e., < 43 ppb/°C). The oscillator circuit shows a worst-case bias instability of 60 ppb and phase noise (PN) of −105 dBc/Hz at 1-kHz offset (Q = 1,700).
{"title":"A 1 MHz 4 ppm CMOS-MEMS oscillator with built-in self-test and sub-mW ovenization power","authors":"Chun-You Liu, Ming-Huang Li, H. Ranjith, Sheng-Shian Li","doi":"10.1109/IEDM.2016.7838488","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838488","url":null,"abstract":"A 1 MHz 4 ppm temperature-stable micro-oven μOven) controlled monolithic CMOS-MEMS oscillator has been demonstrated in this work, exhibiting heating power in sub-mW across the 100°C temperature span. The proposed novel isothermal μOven platform consists of dual heaters, one of which stabilizes the resonator temperature while the other of which serves as built-in self-test (BIST) to mimic ambient temperature, and a resistive temperature detector (RTD) for local resonator temperature monitoring. By adapting the constant-resistance (CR) feedback temperature control scheme, the integrated 1 MHz CMOS-MEMS oscillator shows a maximum frequency inaccuracy of only 4 ppm during a fast temperature ramp across the 94°C testing span (i.e., < 43 ppb/°C). The oscillator circuit shows a worst-case bias instability of 60 ppb and phase noise (PN) of −105 dBc/Hz at 1-kHz offset (Q = 1,700).","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121524152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838467
J. Slaughter, K. Nagel, R. Whig, S. Deshpande, S. Aggarwal, M. Deherrera, J. Janesky, M. Lin, H. Chia, M. Hossain, S. Ikegawa, F. Mancoff, G. Shimon, J. Sun, M. Tran, T. Andre, S. Alam, F. Poh, J. Lee, Y. Chow, Y. Jiang, H. Liu, C. Wang, S. Noh, T. Tahmasebi, S. Ye, D. Shum
In this paper we present an overview of important features for reliable and manufacturable ST-MRAM as well as new results in two areas: pMTJ arrays with data retention sufficient for programming before 260°C wave solder, and performance of a 256Mb, DDR3 ST-MRAM product chip.
{"title":"Technology for reliable spin-torque MRAM products","authors":"J. Slaughter, K. Nagel, R. Whig, S. Deshpande, S. Aggarwal, M. Deherrera, J. Janesky, M. Lin, H. Chia, M. Hossain, S. Ikegawa, F. Mancoff, G. Shimon, J. Sun, M. Tran, T. Andre, S. Alam, F. Poh, J. Lee, Y. Chow, Y. Jiang, H. Liu, C. Wang, S. Noh, T. Tahmasebi, S. Ye, D. Shum","doi":"10.1109/IEDM.2016.7838467","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838467","url":null,"abstract":"In this paper we present an overview of important features for reliable and manufacturable ST-MRAM as well as new results in two areas: pMTJ arrays with data retention sufficient for programming before 260°C wave solder, and performance of a 256Mb, DDR3 ST-MRAM product chip.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124029412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838401
Jiuren Zhou, G. Han, Qinglong Li, Yue Peng, Xiaoli Lu, Chunfu Zhang, Jincheng Zhang, Qingqing Sun, David-Wei Zhang, Y. Hao
We report the first ferroelectric (FE) HfZrOx (HZO) Ge and GeSn pMOSFETs with sub-60 mV/decade subthreshold swing (SS) (40∼43 mV/decade), negligible hysteresis, and enhanced Ids. With a RTA at 450 oC, FE devices with reduced hysteresis of 40∼60 mV demonstrate the significantly improved SS and Ids characteristics compared to control devices without FE, owing to the negative capacitance (NC) effect induced by HZO. FE Ge and GeSn pFETs achieve 22% and 20% Ids enhancement than control devices, respectively, at the drive voltage of 1.0 V. NC effect in FE devices is proved by the gate leakage and inversion capacitance characteristics.
{"title":"Ferroelectric HfZrOx Ge and GeSn PMOSFETs with Sub-60 mV/decade subthreshold swing, negligible hysteresis, and improved Ids","authors":"Jiuren Zhou, G. Han, Qinglong Li, Yue Peng, Xiaoli Lu, Chunfu Zhang, Jincheng Zhang, Qingqing Sun, David-Wei Zhang, Y. Hao","doi":"10.1109/IEDM.2016.7838401","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838401","url":null,"abstract":"We report the first ferroelectric (FE) HfZrOx (HZO) Ge and GeSn pMOSFETs with sub-60 mV/decade subthreshold swing (SS) (40∼43 mV/decade), negligible hysteresis, and enhanced Ids. With a RTA at 450 oC, FE devices with reduced hysteresis of 40∼60 mV demonstrate the significantly improved SS and Ids characteristics compared to control devices without FE, owing to the negative capacitance (NC) effect induced by HZO. FE Ge and GeSn pFETs achieve 22% and 20% Ids enhancement than control devices, respectively, at the drive voltage of 1.0 V. NC effect in FE devices is proved by the gate leakage and inversion capacitance characteristics.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115922585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838408
S. Oda, G. Yamahata, K. Horibe, T. Kodera
Quantum computing is no longer a future technology. Recent advances in D-Wave computers based on quantum annealing and superconducting devices, and the demonstration of long spin decoherence times in isotopically-enriched Si qubits, have accelerated the research and development of this technology. The remaining challenge is large scale integration of qubits. Physically-defined coupled quantum dots (QDs) on silicon-on-insulator substrates represent potential multiple scaled qubits. This work demonstrated the fabrication of coupled QDs with control gates and charge sensor single-electron transistors, the observation of Pauli spin blockade and the control of a few electron regimes, as well as triple QDs and p-channel operation.
{"title":"Coupled quantum dots on SOI as highly integrated Si qubits","authors":"S. Oda, G. Yamahata, K. Horibe, T. Kodera","doi":"10.1109/IEDM.2016.7838408","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838408","url":null,"abstract":"Quantum computing is no longer a future technology. Recent advances in D-Wave computers based on quantum annealing and superconducting devices, and the demonstration of long spin decoherence times in isotopically-enriched Si qubits, have accelerated the research and development of this technology. The remaining challenge is large scale integration of qubits. Physically-defined coupled quantum dots (QDs) on silicon-on-insulator substrates represent potential multiple scaled qubits. This work demonstrated the fabrication of coupled QDs with control gates and charge sensor single-electron transistors, the observation of Pauli spin blockade and the control of a few electron regimes, as well as triple QDs and p-channel operation.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115456306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838533
J. Li, S. Xie, Z. Zheng, Y. Zhang, R. Zhang, M. Xu, Y. Zhao
High performance Ge CMOS with quantum well-structured channels has been successfully realized using a single MoS2 capping layer. Thanks to a large valence band offset (0.43 eV) and conduction band offset (0.5 eV) between the two-layers-thick MoS2 and the Ge substrate, both holes and electrons within the Ge p- and n-MOSFETs are confined into Ge channels and the scattering due to the traps in gate stacks is suppressed effectively. As a result, the MoS2/Ge p- and n-MOSFETs exhibit much improved hole and electron mobilities, as well as the improved device reliability behaviors.
利用单个MoS2封盖层成功实现了具有量子结构良好通道的高性能Ge CMOS。由于两层厚的MoS2和Ge衬底之间存在较大的价带偏移(0.43 eV)和导带偏移(0.5 eV)， Ge p-和n- mosfet内的空穴和电子都被限制在Ge沟道中，栅极堆叠中陷阱引起的散射被有效抑制。结果，MoS2/Ge p-和n- mosfet表现出更好的空穴和电子迁移率，以及更好的器件可靠性行为。
{"title":"High performance and reliability Ge channel CMOS with a MoS2 capping layer","authors":"J. Li, S. Xie, Z. Zheng, Y. Zhang, R. Zhang, M. Xu, Y. Zhao","doi":"10.1109/IEDM.2016.7838533","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838533","url":null,"abstract":"High performance Ge CMOS with quantum well-structured channels has been successfully realized using a single MoS2 capping layer. Thanks to a large valence band offset (0.43 eV) and conduction band offset (0.5 eV) between the two-layers-thick MoS2 and the Ge substrate, both holes and electrons within the Ge p- and n-MOSFETs are confined into Ge channels and the scattering due to the traps in gate stacks is suppressed effectively. As a result, the MoS2/Ge p- and n-MOSFETs exhibit much improved hole and electron mobilities, as well as the improved device reliability behaviors.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"153 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127513396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838031
Rui Tze Toh, Shyam Parthasarathy, T. Sun, Shaoqiang Zhang, Raj Verma Purakh, Chao Song Zhu, Venkata Sudheer Nune, J. S. Wong, M. Govindarajan, Y. K. Yoo, K. Chew, D. Ang
A novel approach to technology integration of system-on-chip RF Front-End Module (FEM) is presented. Device design to achieve best-in-class extended drain power mosfet (EDNMOS) with Ron of 1.6Ohm-mm and fT >39GHz is discussed. This is followed by an analysis of a high performance switch device integrated via selective silicon thinning.
{"title":"A 300mm foundry HRSOI technology with variable silicon thickness for integrated FEM applications","authors":"Rui Tze Toh, Shyam Parthasarathy, T. Sun, Shaoqiang Zhang, Raj Verma Purakh, Chao Song Zhu, Venkata Sudheer Nune, J. S. Wong, M. Govindarajan, Y. K. Yoo, K. Chew, D. Ang","doi":"10.1109/IEDM.2016.7838031","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838031","url":null,"abstract":"A novel approach to technology integration of system-on-chip RF Front-End Module (FEM) is presented. Device design to achieve best-in-class extended drain power mosfet (EDNMOS) with Ron of 1.6Ohm-mm and fT >39GHz is discussed. This is followed by an analysis of a high performance switch device integrated via selective silicon thinning.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127034546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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