Pub Date : 2000-05-22DOI: 10.1109/ISPSD.2000.856796
Y. Hiraoka, S. Matsumoto, T. Sakai
We have compared the radio-frequency performance of quasi-SOI and conventional SOI power MOSFETs based on experimentally obtained results and numerical simulation. The quasi-SOI power MOSFET proved to be superior because the activation of the parasitic bipolar transistor was suppressed. We clarified, through a numerical simulation, that the parasitic bipolar effect causes harmonics generation. Especially, the third-order intermodulation distortion of the quasi-SOI device was about 15 dBc lower than that of the conventional SOI device under 2 GHz operation.
{"title":"Comparison of high-frequency performance of quasi-SOI and conventional SOI power MOSFETs","authors":"Y. Hiraoka, S. Matsumoto, T. Sakai","doi":"10.1109/ISPSD.2000.856796","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856796","url":null,"abstract":"We have compared the radio-frequency performance of quasi-SOI and conventional SOI power MOSFETs based on experimentally obtained results and numerical simulation. The quasi-SOI power MOSFET proved to be superior because the activation of the parasitic bipolar transistor was suppressed. We clarified, through a numerical simulation, that the parasitic bipolar effect causes harmonics generation. Especially, the third-order intermodulation distortion of the quasi-SOI device was about 15 dBc lower than that of the conventional SOI device under 2 GHz operation.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125657462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-22DOI: 10.1109/ISPSD.2000.856848
Jongdae Kim, T. Rob, Sang-Gi Kim, Q. Song, J. Koo, K. Nam, K. Cho, D. Ma
A new process technique for fabricating very high-density trench MOSFETs using 4 mask layers with oxide spacers and self-align technique is realized. This technique reduces the process steps, trench width, and source and p-body region with a resulting increase in cell density and current driving capability, and decrease in on-resistance as well as cost-effective production capability. Specific on-resistance of 0.41 m/spl Omega/.cm/sup 2/ with a blocking voltage of 43 is obtained.
{"title":"High-density low on-resistance trench MOSFETs employing oxide spacers and self-align technique for DC/DC converter","authors":"Jongdae Kim, T. Rob, Sang-Gi Kim, Q. Song, J. Koo, K. Nam, K. Cho, D. Ma","doi":"10.1109/ISPSD.2000.856848","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856848","url":null,"abstract":"A new process technique for fabricating very high-density trench MOSFETs using 4 mask layers with oxide spacers and self-align technique is realized. This technique reduces the process steps, trench width, and source and p-body region with a resulting increase in cell density and current driving capability, and decrease in on-resistance as well as cost-effective production capability. Specific on-resistance of 0.41 m/spl Omega/.cm/sup 2/ with a blocking voltage of 43 is obtained.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132759246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-22DOI: 10.1109/ISPSD.2000.856815
F. Heinke, R. Sittig
A new power semiconductor device is introduced which facilitates bidirectional operation. Numerical simulations predict excellent stationary characteristics up to high temperatures. Moreover under all operation conditions the device allows one to adjust the distribution of the electron hole plasma. For instance during turn-off it is possible to control the rate of current decay and the corresponding overvoltage peak.
{"title":"The monolithic bidirectional switch (MBS)","authors":"F. Heinke, R. Sittig","doi":"10.1109/ISPSD.2000.856815","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856815","url":null,"abstract":"A new power semiconductor device is introduced which facilitates bidirectional operation. Numerical simulations predict excellent stationary characteristics up to high temperatures. Moreover under all operation conditions the device allows one to adjust the distribution of the electron hole plasma. For instance during turn-off it is possible to control the rate of current decay and the corresponding overvoltage peak.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133280326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-22DOI: 10.1109/ISPSD.2000.856766
F. Bauer, N. Kaminski, S. Linder, H. Zeller
This paper presents the experimental characteristics of a high voltage IGBT and diode chip set designed for safe operation under hard switching conditions at the 2.8 kV DC link level. The fundamental goal of the design is a low cosmic ray induced failure rate for diodes as well as IGBTs at the DC link level. At the same time all the common requirements of low static and dynamic losses as well as wide SOA under turn-off, reverse recovery and short-circuit conditions are fulfilled. The blocking capability of these devices exceeds 4.5 kV by far.
{"title":"A high voltage IGBT and diode chip set designed for the 2.8 kV DC link level with short circuit capability extending to the maximum blocking voltage","authors":"F. Bauer, N. Kaminski, S. Linder, H. Zeller","doi":"10.1109/ISPSD.2000.856766","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856766","url":null,"abstract":"This paper presents the experimental characteristics of a high voltage IGBT and diode chip set designed for safe operation under hard switching conditions at the 2.8 kV DC link level. The fundamental goal of the design is a low cosmic ray induced failure rate for diodes as well as IGBTs at the DC link level. At the same time all the common requirements of low static and dynamic losses as well as wide SOA under turn-off, reverse recovery and short-circuit conditions are fulfilled. The blocking capability of these devices exceeds 4.5 kV by far.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131517373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-22DOI: 10.1109/ISPSD.2000.856778
K. Nakamura, S. Kusunoki, H. Nakamura, M. Harada
We have done research for the purpose of improving the reliability of trench MOS gate devices that utilize trench gate oxide over 10 nm in thickness. This paper reports, for the first time, that the CVD gate oxide (CGO) film is much more effective as a gate dielectric for use in trench MOS gate devices than the thermal oxide widely used in the SiO/sub 2/ gate dielectric of MOS gate devices. Our results show that the electrical characteristics (leakage characteristic and Time-Zero Dielectric Breakdown characteristic), the reliability and current drivability of trench MOS gate devices can be dramatically improved by CVD gate oxide (especially oxynitride CGO). These improvements are caused by the excellent uniformity of thickness and the good quality of gate oxide which formed on an inner trench with the specific geometrical factor. From the viewpoint of insuring the reliability for large trench capacitor area, this new CGO dielectric is a promising candidate for trench MOS gate power devices.
{"title":"Advantages of thick CVD gate oxide for trench MOS gate structures","authors":"K. Nakamura, S. Kusunoki, H. Nakamura, M. Harada","doi":"10.1109/ISPSD.2000.856778","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856778","url":null,"abstract":"We have done research for the purpose of improving the reliability of trench MOS gate devices that utilize trench gate oxide over 10 nm in thickness. This paper reports, for the first time, that the CVD gate oxide (CGO) film is much more effective as a gate dielectric for use in trench MOS gate devices than the thermal oxide widely used in the SiO/sub 2/ gate dielectric of MOS gate devices. Our results show that the electrical characteristics (leakage characteristic and Time-Zero Dielectric Breakdown characteristic), the reliability and current drivability of trench MOS gate devices can be dramatically improved by CVD gate oxide (especially oxynitride CGO). These improvements are caused by the excellent uniformity of thickness and the good quality of gate oxide which formed on an inner trench with the specific geometrical factor. From the viewpoint of insuring the reliability for large trench capacitor area, this new CGO dielectric is a promising candidate for trench MOS gate power devices.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"2015 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127777837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-22DOI: 10.1109/ISPSD.2000.856828
C. Hager, A. Stuck, Y. Tronel, R. Zehringer, W. Fichtner
Coffin-Manson fatigue law based lifetime estimations of aluminum bond wires in IGBT modules under field conditions were performed. The models were calibrated with fatigue data obtained from accelerated lifetime tests and plastic strain computations corresponding to test conditions. The calibrated laws were then used to predict the bond wire lifetime under field conditions. To evaluate the influence of the plastic strain calculations, finite-element and analytical computations were performed and the resulting lifetimes compared.
{"title":"Comparison between finite-element and analytical calculations for the lifetime estimation of bond wires in IGBT modules","authors":"C. Hager, A. Stuck, Y. Tronel, R. Zehringer, W. Fichtner","doi":"10.1109/ISPSD.2000.856828","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856828","url":null,"abstract":"Coffin-Manson fatigue law based lifetime estimations of aluminum bond wires in IGBT modules under field conditions were performed. The models were calibrated with fatigue data obtained from accelerated lifetime tests and plastic strain computations corresponding to test conditions. The calibrated laws were then used to predict the bond wire lifetime under field conditions. To evaluate the influence of the plastic strain calculations, finite-element and analytical computations were performed and the resulting lifetimes compared.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133657811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-22DOI: 10.1109/ISPSD.2000.856810
P. Shenoy, J. Yedinak, J. Gladish
In this paper, we report for the first time, the measured characteristics of a low loss, high speed IGBT designed for 300 V operation. The optimized 300 V IGBTs exhibit a low Vce/sub (sat)/ of 1.35 V and an extremely fast fall time of less than 20 ns at a current density of 120 A/cm/sup 2/ and a junction temperature of 150/spl deg/C. This extremely fast switching results in an E/sub off/ of less than 5 /spl mu/J/A at 150/spl deg/C which is comparable to that of a MOSFET. The IGBT has a maximum operating frequency of greater than 400 kHz at rated current. These new 300 V IGBTs exhibit lower total losses than a 250 V MOSFET at operating frequencies as high as 350 kHz. The IGBT is also optimized for UIS capability and has a single pulse avalanche energy capability in excess of 3 J/cm/sup 2/ at rated current.
本文首次报道了设计用于300v工作的低损耗、高速IGBT的实测特性。优化后的300 V igbt在电流密度为120 a /cm/sup 2/、结温为150/spl℃时，Vce/sub (sat)/低至1.35 V，下降时间小于20 ns。这种极快的开关导致在150/spl度/C下的E/sub关断小于5 /spl mu/J/A，这与MOSFET相当。IGBT在额定电流下的最大工作频率大于400khz。在高达350 kHz的工作频率下，这些新的300 V igbt比250 V MOSFET具有更低的总损耗。IGBT还针对UIS能力进行了优化，在额定电流下具有超过3 J/cm/sup 2/的单脉冲雪崩能量能力。
{"title":"High performance 300 V IGBTs","authors":"P. Shenoy, J. Yedinak, J. Gladish","doi":"10.1109/ISPSD.2000.856810","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856810","url":null,"abstract":"In this paper, we report for the first time, the measured characteristics of a low loss, high speed IGBT designed for 300 V operation. The optimized 300 V IGBTs exhibit a low Vce/sub (sat)/ of 1.35 V and an extremely fast fall time of less than 20 ns at a current density of 120 A/cm/sup 2/ and a junction temperature of 150/spl deg/C. This extremely fast switching results in an E/sub off/ of less than 5 /spl mu/J/A at 150/spl deg/C which is comparable to that of a MOSFET. The IGBT has a maximum operating frequency of greater than 400 kHz at rated current. These new 300 V IGBTs exhibit lower total losses than a 250 V MOSFET at operating frequencies as high as 350 kHz. The IGBT is also optimized for UIS capability and has a single pulse avalanche energy capability in excess of 3 J/cm/sup 2/ at rated current.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132281235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-22DOI: 10.1109/ISPSD.2000.856834
V. Parthasarathy, R. Zhu, M. Ger, V. Khemka, A. Bose, R. Baird, T. Roggenbauer, D. Collins, S. Chang, P. Hui, M. Zunino
This paper describes a 0.35 /spl mu/m smart power technology that enables integration of a diverse set of analog and high-voltage power components in a 0.35 /spl mu/m CMOS logic platform for a broad range of voltage applications from 7 V to 50 V.
{"title":"A 0.35 /spl mu/m CMOS based smart power technology for 7 V-50 V applications","authors":"V. Parthasarathy, R. Zhu, M. Ger, V. Khemka, A. Bose, R. Baird, T. Roggenbauer, D. Collins, S. Chang, P. Hui, M. Zunino","doi":"10.1109/ISPSD.2000.856834","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856834","url":null,"abstract":"This paper describes a 0.35 /spl mu/m smart power technology that enables integration of a diverse set of analog and high-voltage power components in a 0.35 /spl mu/m CMOS logic platform for a broad range of voltage applications from 7 V to 50 V.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132761611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-22DOI: 10.1109/ISPSD.2000.856829
N. Iwamuro, F. Nagaune, T. Iwaana, Y. Seki
A novel free wheeling diode with its blocking capability of 1700 V is presented to realize an excellent trade-off characteristic between a forward voltage drop and a reverse recovery loss, for the first time. A superior forward voltage drop (Vf) of 1.85 V with the reverse recovery loss (Err) of 13.0 mJ is successfully achieved (a rated current is set at 100 amperes). These values of Vf and Err indicate the much superior trade-off characteristic to the conventional FWD. Furthermore, it should be noted that the newly developed FWD achieves a positive temperature coefficient of Vf, which is more advantageous for parallel connection of an IGBT module.
{"title":"A novel free wheeling diode for 1700 V IGBT module","authors":"N. Iwamuro, F. Nagaune, T. Iwaana, Y. Seki","doi":"10.1109/ISPSD.2000.856829","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856829","url":null,"abstract":"A novel free wheeling diode with its blocking capability of 1700 V is presented to realize an excellent trade-off characteristic between a forward voltage drop and a reverse recovery loss, for the first time. A superior forward voltage drop (Vf) of 1.85 V with the reverse recovery loss (Err) of 13.0 mJ is successfully achieved (a rated current is set at 100 amperes). These values of Vf and Err indicate the much superior trade-off characteristic to the conventional FWD. Furthermore, it should be noted that the newly developed FWD achieves a positive temperature coefficient of Vf, which is more advantageous for parallel connection of an IGBT module.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114257294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-22DOI: 10.1109/ISPSD.2000.856769
S. Nassif-Khalil, S. Honarkhah, C. Salama
1 A lateral Power MOSFET switch, implemented in a 0.25 /spl mu/m-5 metal CMOS process and suitable for high-frequency switch mode on-chip DC/DC converters is described in this paper. The fabricated device has an active chip area of 130 /spl mu/m/spl times/130 /spl mu/m and exhibits an on-resistance of 40.37 m/spl Omega/ (a specific on-resistance of 6.82 /spl mu//spl Omega/cm/sup 2/) and a total gate charge of 0.105 nC at V/sub GS/=3.3 V.
{"title":"Low voltage CMOS compatible power MOSFET for on-chip DC/DC converters","authors":"S. Nassif-Khalil, S. Honarkhah, C. Salama","doi":"10.1109/ISPSD.2000.856769","DOIUrl":"https://doi.org/10.1109/ISPSD.2000.856769","url":null,"abstract":"1 A lateral Power MOSFET switch, implemented in a 0.25 /spl mu/m-5 metal CMOS process and suitable for high-frequency switch mode on-chip DC/DC converters is described in this paper. The fabricated device has an active chip area of 130 /spl mu/m/spl times/130 /spl mu/m and exhibits an on-resistance of 40.37 m/spl Omega/ (a specific on-resistance of 6.82 /spl mu//spl Omega/cm/sup 2/) and a total gate charge of 0.105 nC at V/sub GS/=3.3 V.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114365104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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