Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307483
J. Hayden, M. Woo, R. Taft, P. Pelley, B. Nguyen, C. Mazure, P. Kenkare, K. Kemp, R. Subrahmanyan, A. Sitaram, J. Lin, J. Ko, C. King, C. Gunderson, H. Kirsch
An advanced, high-performance BiCMOS technology has been developed for fast 16Mb SRAMs. A split word-line bitcell architecture, using four levels of polysilicon and two self-aligned contacts, achieves a cell area of 8.61 mu m/sup 2/ with conventional i-line lithography and 7.32 mu m/sup 2/ with i-line phase-shift lithography. The process features PELOX isolation to provide a 1.0 mu m active pitch, MOSFET transistors designed for a 0.80 mu m gate poly pitch, a double polysilicon bipolar transistor with aggressively scaled parasitics, and a thin-film polysilicon transistor to enhance bitcell stability. A quadruple-well structure improves soft error rate (SER) and allows simultaneous optimization of MOSFET and bipolar performance,.<>
{"title":"A high-performance quadruple well, quadruple poly BiCMOS process for fast 16 Mb SRAMs","authors":"J. Hayden, M. Woo, R. Taft, P. Pelley, B. Nguyen, C. Mazure, P. Kenkare, K. Kemp, R. Subrahmanyan, A. Sitaram, J. Lin, J. Ko, C. King, C. Gunderson, H. Kirsch","doi":"10.1109/IEDM.1992.307483","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307483","url":null,"abstract":"An advanced, high-performance BiCMOS technology has been developed for fast 16Mb SRAMs. A split word-line bitcell architecture, using four levels of polysilicon and two self-aligned contacts, achieves a cell area of 8.61 mu m/sup 2/ with conventional i-line lithography and 7.32 mu m/sup 2/ with i-line phase-shift lithography. The process features PELOX isolation to provide a 1.0 mu m active pitch, MOSFET transistors designed for a 0.80 mu m gate poly pitch, a double polysilicon bipolar transistor with aggressively scaled parasitics, and a thin-film polysilicon transistor to enhance bitcell stability. A quadruple-well structure improves soft error rate (SER) and allows simultaneous optimization of MOSFET and bipolar performance,.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125151009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307478
T. Hamada, N. Tanabe, H. Watanabe, K. Takeuchi, N. Kasai, H. Hada, K. Shibahara, K. Tokashiki, K. Nakajima, S. Hirasawa, E. Ikawa, T. Saeki, E. Kakehashi, S. Ohya, T. Kunio
A Split-Level Diagonal Bit-line (SLDB) stacked capacitor cell having a cylindrical storage node with hemispherical grained (HSG) silicon is proposed for 256 MbDRAMs. This memory cell provides large alignment tolerance between contact hole and wiring, large word-line noise immunity and large storage capacitance in a small cell area of 0.54 mu m/sup 2/ with 0.25 mu m design rule.<>
{"title":"A Split-Level Diagonal Bit-line (SLDB) stacked capacitor cell for 256 Mb DRAMs","authors":"T. Hamada, N. Tanabe, H. Watanabe, K. Takeuchi, N. Kasai, H. Hada, K. Shibahara, K. Tokashiki, K. Nakajima, S. Hirasawa, E. Ikawa, T. Saeki, E. Kakehashi, S. Ohya, T. Kunio","doi":"10.1109/IEDM.1992.307478","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307478","url":null,"abstract":"A Split-Level Diagonal Bit-line (SLDB) stacked capacitor cell having a cylindrical storage node with hemispherical grained (HSG) silicon is proposed for 256 MbDRAMs. This memory cell provides large alignment tolerance between contact hole and wiring, large word-line noise immunity and large storage capacitance in a small cell area of 0.54 mu m/sup 2/ with 0.25 mu m design rule.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125137242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307461
X. L. Wang, V. Chandramouli, C. Maziar, A. Tasch
A new impact ionization model for our multi-band Monte Carlo simulator SLAPSHOT (Simulation Program Suitable for Hot Carrier Studies) is described in this paper. The new model, based on a modified anisotropic Keldysh formula, uses a threshold energy calculated by invoking both energy and momentum conservation in full pseudopotential bands. The new model is used, together with experimental impact ionization data, to accurately estimate the extent of the high energy tail of the energy distribution function and appropriate electron-phonon coupling constants for use in second energy band carrier transport descriptions.<>
{"title":"An efficient multi-band Monte Carlo model with anisotropic impact ionization","authors":"X. L. Wang, V. Chandramouli, C. Maziar, A. Tasch","doi":"10.1109/IEDM.1992.307461","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307461","url":null,"abstract":"A new impact ionization model for our multi-band Monte Carlo simulator SLAPSHOT (Simulation Program Suitable for Hot Carrier Studies) is described in this paper. The new model, based on a modified anisotropic Keldysh formula, uses a threshold energy calculated by invoking both energy and momentum conservation in full pseudopotential bands. The new model is used, together with experimental impact ionization data, to accurately estimate the extent of the high energy tail of the energy distribution function and appropriate electron-phonon coupling constants for use in second energy band carrier transport descriptions.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114277988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307484
C. T. Liu, K. H. Lee, C.-H.D. Yu, J. Sung, W. Nagy, A. Kornblit, T. Kook, K. Olasupo, R. Druckenmiller, C. Fu, S. Molloy
A simple self-aligned LDD structure is utilized in gate-inverted TFT's. The process is simple, and satisfactory reliability/uniformity is obtained. Consequently, the high performance devices are applicable to 16 Mbit SRAM's or beyond. We report on the following: fabrication of the devices integrated into our SRAM cells; the I-V characteristics of 0.35 mu m*0.35 mu m devices and their aging and temperature performance; a high I/sub ON//I/sub OFF/ ratio of 1.2*10/sup 8/ achieved without rapid thermal annealing or plasma hydrogenation; the uniformity of I/sub ON/; and considerations of device scaling and process margins.<>
{"title":"High reliability and high performance 0.35 mu m gate-inverted TFT's for 16 Mbit SRAM applications using self-aligned LDD structures","authors":"C. T. Liu, K. H. Lee, C.-H.D. Yu, J. Sung, W. Nagy, A. Kornblit, T. Kook, K. Olasupo, R. Druckenmiller, C. Fu, S. Molloy","doi":"10.1109/IEDM.1992.307484","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307484","url":null,"abstract":"A simple self-aligned LDD structure is utilized in gate-inverted TFT's. The process is simple, and satisfactory reliability/uniformity is obtained. Consequently, the high performance devices are applicable to 16 Mbit SRAM's or beyond. We report on the following: fabrication of the devices integrated into our SRAM cells; the I-V characteristics of 0.35 mu m*0.35 mu m devices and their aging and temperature performance; a high I/sub ON//I/sub OFF/ ratio of 1.2*10/sup 8/ achieved without rapid thermal annealing or plasma hydrogenation; the uniformity of I/sub ON/; and considerations of device scaling and process margins.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"83 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122624318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307312
A. Feygenson, R. Hamm, P. Smith, M. Pinto, R. Montgomery, R. D. Yadvish, H. Temkin
We describe a composite collector InP/InGaAs heterostructure bipolar transistor with f/sub T/=144 GHz and f/sub max/=81 GHz. The breakdown voltage BV/sub CEO/ is greater than 5V and output conductance is essentially independent of the collector voltage. This combination of performance characteristics is obtained with a carefully optimized collector structure. A monolithic transimpedance amplifier based on composite collector transistors has a bandwidth of 28 GHz and gain of 40 dB Omega . A hybrid optical receiver constructed with these amplifiers has open eye diagrams at 32 Gbit/s and a 1*10/sup -9/ error rate with -23.7 dBm of incident power.<>
{"title":"A 144 GHz InP/InGaAs composite collector heterostructure bipolar transistor","authors":"A. Feygenson, R. Hamm, P. Smith, M. Pinto, R. Montgomery, R. D. Yadvish, H. Temkin","doi":"10.1109/IEDM.1992.307312","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307312","url":null,"abstract":"We describe a composite collector InP/InGaAs heterostructure bipolar transistor with f/sub T/=144 GHz and f/sub max/=81 GHz. The breakdown voltage BV/sub CEO/ is greater than 5V and output conductance is essentially independent of the collector voltage. This combination of performance characteristics is obtained with a carefully optimized collector structure. A monolithic transimpedance amplifier based on composite collector transistors has a bandwidth of 28 GHz and gain of 40 dB Omega . A hybrid optical receiver constructed with these amplifiers has open eye diagrams at 32 Gbit/s and a 1*10/sup -9/ error rate with -23.7 dBm of incident power.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122208820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307375
J. Hwang, G. Pollack
Fully-depleted SOI/CMOS transistors were fabricated using titanium-nitride (TiN) gates with near midgap work-function in order to optimize the p- and n-channel threshold voltages for operation at low supply voltage. To simplify the process as well as to minimize the strain, a novel gate structure was used in which a thick polysilicon (300 nm) was stacked on a thin TiN layer (<50 nm). Excellent symmetrical subthreshold characteristics were obtained with relatively low values of threshold voltage and low off-state leakages. The subthreshold swing, transconductance, and saturation drain current were comparable with those for conventional n/sup +//p/sup +/ polysilicon gates. In addition, hot-carrier stress results indicate no significant differences from the poly-gate cases.<>
{"title":"Novel polysilicon/TiN stacked-gate structure for fully-depleted SOI/CMOS","authors":"J. Hwang, G. Pollack","doi":"10.1109/IEDM.1992.307375","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307375","url":null,"abstract":"Fully-depleted SOI/CMOS transistors were fabricated using titanium-nitride (TiN) gates with near midgap work-function in order to optimize the p- and n-channel threshold voltages for operation at low supply voltage. To simplify the process as well as to minimize the strain, a novel gate structure was used in which a thick polysilicon (300 nm) was stacked on a thin TiN layer (<50 nm). Excellent symmetrical subthreshold characteristics were obtained with relatively low values of threshold voltage and low off-state leakages. The subthreshold swing, transconductance, and saturation drain current were comparable with those for conventional n/sup +//p/sup +/ polysilicon gates. In addition, hot-carrier stress results indicate no significant differences from the poly-gate cases.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123053091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307522
W. Jiang, U. Mishra
Hot electron emission from a planar surface has been pursued in the past two decades in both silicon and III-V compound semiconductors. Since they are majority carrier devices and have controllable material growth by MBE, emitters made from planar doped barrier (PDB) structures have the advantages of high current density and high electron emission efficiency. The authors present the emission from a new Al/sub 0.3/Ga/sub 0.7/As-GaAs PDB emitter. A PDB structure consists of a sequence of n/sup +/-i-p/sup +/(delta-doped)-i-n/sup +/ layers. The p/sup +/ delta-doped sheet is fully depleted giving rise to a triangular barrier. A positive bias applied to the surface forward biases the n/sup +/-i-p/sup +/ injecting junction and reverse biases the p/sup +/-i-n/sup +/ accelerating junction so that electrons in the n/sup +/ region are injected across the barrier into a high field region and accelerated toward the surface. Electrons with kinetic energy larger than the surface work function are then emitted. For an efficient PDB emitter, the transit distance (the total thickness of the accelerating region and the top contact layer) should be small and the accelerating voltage (the voltage drop across the accelerating region) should be large. The breakdown of the accelerating junction sets an upper limit to the field applied to the accelerating region. One way to increase the accelerating voltage and hence the electron kinetic energy, without sacrificing the small transit distance, is using materials with a higher breakdown field.<>
{"title":"A novel electron emitter with AlGaAs planar doped barrier","authors":"W. Jiang, U. Mishra","doi":"10.1109/IEDM.1992.307522","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307522","url":null,"abstract":"Hot electron emission from a planar surface has been pursued in the past two decades in both silicon and III-V compound semiconductors. Since they are majority carrier devices and have controllable material growth by MBE, emitters made from planar doped barrier (PDB) structures have the advantages of high current density and high electron emission efficiency. The authors present the emission from a new Al/sub 0.3/Ga/sub 0.7/As-GaAs PDB emitter. A PDB structure consists of a sequence of n/sup +/-i-p/sup +/(delta-doped)-i-n/sup +/ layers. The p/sup +/ delta-doped sheet is fully depleted giving rise to a triangular barrier. A positive bias applied to the surface forward biases the n/sup +/-i-p/sup +/ injecting junction and reverse biases the p/sup +/-i-n/sup +/ accelerating junction so that electrons in the n/sup +/ region are injected across the barrier into a high field region and accelerated toward the surface. Electrons with kinetic energy larger than the surface work function are then emitted. For an efficient PDB emitter, the transit distance (the total thickness of the accelerating region and the top contact layer) should be small and the accelerating voltage (the voltage drop across the accelerating region) should be large. The breakdown of the accelerating junction sets an upper limit to the field applied to the accelerating region. One way to increase the accelerating voltage and hence the electron kinetic energy, without sacrificing the small transit distance, is using materials with a higher breakdown field.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122417346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307415
J. Rodriguez, R. C. Hughes, W. Corbett, P. McWhorter
A new robust, wide-range hydrogen sensor technology integrates catalytic gate transistors and resistors with a baseline CMOS process. Pd or PdNi gate transistors detect low concentrations of hydrogen (ppm) and Pd or PdNi thin film resistors sense higher concentrations of hydrogen (up to 100%). Fabrication of both sensors on the same die allows detection of hydrogen over a dynamic range of 6 orders of magnitude. On-chip power transistor heaters and diode thermometers allow accurate chip temperature control.<>
{"title":"Robust, wide range hydrogen sensor","authors":"J. Rodriguez, R. C. Hughes, W. Corbett, P. McWhorter","doi":"10.1109/IEDM.1992.307415","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307415","url":null,"abstract":"A new robust, wide-range hydrogen sensor technology integrates catalytic gate transistors and resistors with a baseline CMOS process. Pd or PdNi gate transistors detect low concentrations of hydrogen (ppm) and Pd or PdNi thin film resistors sense higher concentrations of hydrogen (up to 100%). Fabrication of both sensors on the same die allows detection of hydrogen over a dynamic range of 6 orders of magnitude. On-chip power transistor heaters and diode thermometers allow accurate chip temperature control.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124417834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307450
M. Mohri, H. Kakinuma, T. Tsuruoka
Polycrystalline-Si (poly-Si) films prepared by conventional plasma CVD with SiF/sub 4//SiH/sub 4//H/sub 2/ gases at a very low temperature (300 degrees C) have been applied to thin film transistors (TFTs). The thickness dependance of crystallinity and the surface morphology are characterized. Top gate coplanar TFT have been fabricated with optimized poly-Si. The characteristics are improved by annealing (400 degrees C). It increased the field effect mobility ( mu /sub e/) to 10.1 cm/sup 2//Vs and reduced off current (I/sub off/) by more than one order of magnitude.<>
{"title":"Fabrication of TFTs using plasma CVD poly-Si at very low temperature","authors":"M. Mohri, H. Kakinuma, T. Tsuruoka","doi":"10.1109/IEDM.1992.307450","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307450","url":null,"abstract":"Polycrystalline-Si (poly-Si) films prepared by conventional plasma CVD with SiF/sub 4//SiH/sub 4//H/sub 2/ gases at a very low temperature (300 degrees C) have been applied to thin film transistors (TFTs). The thickness dependance of crystallinity and the surface morphology are characterized. Top gate coplanar TFT have been fabricated with optimized poly-Si. The characteristics are improved by annealing (400 degrees C). It increased the field effect mobility ( mu /sub e/) to 10.1 cm/sup 2//Vs and reduced off current (I/sub off/) by more than one order of magnitude.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124564791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307411
C. Nguyen, Roger T. IAowe
The implementation of very high Q microelectromechanical filters, constructed of spring-coupled or parallel resonators, requires strict control over the quality factor of the constituent resonators. This report details electrostatic feedback techniques which allow precise control of the quality factor of a micromechanical resonator device, independent of the ambient operating pressure of the micromechanical system. Theoretical formulas governing Q-control are derived and experimentally verified.<>
{"title":"Quality factor control for micromechanical resonators","authors":"C. Nguyen, Roger T. IAowe","doi":"10.1109/IEDM.1992.307411","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307411","url":null,"abstract":"The implementation of very high Q microelectromechanical filters, constructed of spring-coupled or parallel resonators, requires strict control over the quality factor of the constituent resonators. This report details electrostatic feedback techniques which allow precise control of the quality factor of a micromechanical resonator device, independent of the ambient operating pressure of the micromechanical system. Theoretical formulas governing Q-control are derived and experimentally verified.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128940948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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