Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307322
D. V. Rossi, A. Cheng, H. Wieder, E. Fossum
The first two-dimensional electron gas (2DEG) charge-coupled device (CCD) fabricated in the In/sub 0.52/Al/sub 0.48/As/In/sub 0.53/Ga/sub 0.47/As/InP materials system is reported. The device is implemented as a 31-stage, four-phase, resistive-gate delay line, and features an on-chip 2DEG-FET source-follower. The per-transfer efficiency is measured to be 0.995.<>
报道了首个在in /sub 0.52/Al/sub 0.48/As/ in /sub 0.53/Ga/sub 0.47/As/InP材料体系中制备的二维电子气电荷耦合器件(CCD)。该器件实现为31级、四相、电阻门延迟线，并具有片上2DEG-FET源-跟随器。每次传输效率为0.995.>
{"title":"A resistive-gate InAlAs/InGaAs/InP 2DEG CCD","authors":"D. V. Rossi, A. Cheng, H. Wieder, E. Fossum","doi":"10.1109/IEDM.1992.307322","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307322","url":null,"abstract":"The first two-dimensional electron gas (2DEG) charge-coupled device (CCD) fabricated in the In/sub 0.52/Al/sub 0.48/As/In/sub 0.53/Ga/sub 0.47/As/InP materials system is reported. The device is implemented as a 31-stage, four-phase, resistive-gate delay line, and features an on-chip 2DEG-FET source-follower. The per-transfer efficiency is measured to be 0.995.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116320596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307439
H. Soleimani, A. Philipossian, B. Doyle
The results of thermal oxidation studies in N/sub 2/O on P
N/sub /O对P的热氧化研究结果
{"title":"A study of the growth kinetics of SiO/sub 2/ in N/sub 2/O(for MOSFETs)","authors":"H. Soleimani, A. Philipossian, B. Doyle","doi":"10.1109/IEDM.1992.307439","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307439","url":null,"abstract":"The results of thermal oxidation studies in N/sub 2/O on P","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"19 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116749262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307394
K. Kotani, T. Shibata, T. Ohmi
We have developed a new binary-logic circuit scheme in which a highly-functional device called a neuron MOS transistor (vMOS) is utilized as a key component. A dramatic reduction in the number of transistors as well as in the complexity of interconnections has been achieved by the new circuit configuration using vMOS. Operational principles and design techniques of vMOS binary-logic circuits are described. The operation of the designed circuits has been experimentally verified by fabricating test circuits using a standard double-polysilicon CMOS process.<>
{"title":"Neuron-MOS binary-logic circuits featuring dramatic reduction in transistor count and interconnections","authors":"K. Kotani, T. Shibata, T. Ohmi","doi":"10.1109/IEDM.1992.307394","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307394","url":null,"abstract":"We have developed a new binary-logic circuit scheme in which a highly-functional device called a neuron MOS transistor (vMOS) is utilized as a key component. A dramatic reduction in the number of transistors as well as in the complexity of interconnections has been achieved by the new circuit configuration using vMOS. Operational principles and design techniques of vMOS binary-logic circuits are described. The operation of the designed circuits has been experimentally verified by fabricating test circuits using a standard double-polysilicon CMOS process.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117282684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307486
A. Perera, C. Lage, A. Sitaram, M. Woo, S. Tatti
Using TiSi/sub 2/ to strap polysilicon over severe topography is hampered by the non-conformality of sputter deposited titanium (Ti) films. Thinning of the Ti translates into regions with thin silicide which degrade drastically when subject to 900 degrees C anneals. Etching back a thick polysilicon film to the desired thickness planarizes the surface for Ti deposition and eliminates the influence of underlying topography. The fabrication process outlined provides a final TiSi/sub 2/ sheet resistance approximately 2 Omega / Square Operator , after a 900 degrees C anneal in O/sub 2/.<>
{"title":"Thermally robust TiSi/sub 2/ on heavily doped polycrystalline silicon over severe topography","authors":"A. Perera, C. Lage, A. Sitaram, M. Woo, S. Tatti","doi":"10.1109/IEDM.1992.307486","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307486","url":null,"abstract":"Using TiSi/sub 2/ to strap polysilicon over severe topography is hampered by the non-conformality of sputter deposited titanium (Ti) films. Thinning of the Ti translates into regions with thin silicide which degrade drastically when subject to 900 degrees C anneals. Etching back a thick polysilicon film to the desired thickness planarizes the surface for Ti deposition and eliminates the influence of underlying topography. The fabrication process outlined provides a final TiSi/sub 2/ sheet resistance approximately 2 Omega / Square Operator , after a 900 degrees C anneal in O/sub 2/.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127339656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307396
Chung-Yu Wu, Chin-Fong Chiu
A new silicon retina structure in CMOS is proposed and analyzed, which incorporates a parasitic phototransistor as an isolated photoreceptor with many phototransistors in a common well region. The smooth function is achieved by the diffusion of photogenerated carriers in the common well. Experimental results have verified the correct functions of the new structure as a silicon retina. Small chip area and compact wiring make the new structure quite realizable with the associated neural networks in VLSI.<>
{"title":"A new structure for the silicon retina","authors":"Chung-Yu Wu, Chin-Fong Chiu","doi":"10.1109/IEDM.1992.307396","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307396","url":null,"abstract":"A new silicon retina structure in CMOS is proposed and analyzed, which incorporates a parasitic phototransistor as an isolated photoreceptor with many phototransistors in a common well region. The smooth function is achieved by the diffusion of photogenerated carriers in the common well. Experimental results have verified the correct functions of the new structure as a silicon retina. Small chip area and compact wiring make the new structure quite realizable with the associated neural networks in VLSI.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127061889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307463
P. Ciampolini, A. Pierantoni, G. Baccarani
In this paper a new model, aimed at modeling heat transport in silicon devices, is presented. It relies on three energy-balance equations, derived for electrons, holes and the lattice. By means of proper assumptions, a single equation is worked out, which supplements the "standard" semiconductor equations and provides an accurate, yet simple, model, suitable for numerical simulation of non-isothermal regimes. Full 3D implementation of such a model has been carried out, and some results of electrothermal simulation are discussed.<>
{"title":"An energy-balance model for non-isothermal device simulation","authors":"P. Ciampolini, A. Pierantoni, G. Baccarani","doi":"10.1109/IEDM.1992.307463","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307463","url":null,"abstract":"In this paper a new model, aimed at modeling heat transport in silicon devices, is presented. It relies on three energy-balance equations, derived for electrons, holes and the lattice. By means of proper assumptions, a single equation is worked out, which supplements the \"standard\" semiconductor equations and provides an accurate, yet simple, model, suitable for numerical simulation of non-isothermal regimes. Full 3D implementation of such a model has been carried out, and some results of electrothermal simulation are discussed.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"288 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125882841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307405
K. Gullapalli, A. Tsao, D. Neikirk
Based on a coherent tunneling calculation, we have found multiple self-consistent solutions, even at zero bias, in diodes that combine a tunneling heterostructure with an N/sup -/-N/sup +/-N/sup -/ spacer layer. We have also experimentally observed multiple stable I-V curves in such devices grown in the GaAs/AlAs material system using molecular beam epitaxy. The I-V curves corresponding to the different states remain distinct and separated through zero bias. The device can be repetitively switched between states and maintains memory of its state even under short circuit conditions.<>
{"title":"Observation of zero-bias multi-state behavior in selectively doped two-terminal quantum tunneling devices","authors":"K. Gullapalli, A. Tsao, D. Neikirk","doi":"10.1109/IEDM.1992.307405","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307405","url":null,"abstract":"Based on a coherent tunneling calculation, we have found multiple self-consistent solutions, even at zero bias, in diodes that combine a tunneling heterostructure with an N/sup -/-N/sup +/-N/sup -/ spacer layer. We have also experimentally observed multiple stable I-V curves in such devices grown in the GaAs/AlAs material system using molecular beam epitaxy. The I-V curves corresponding to the different states remain distinct and separated through zero bias. The device can be repetitively switched between states and maintains memory of its state even under short circuit conditions.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125903461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307513
T. L. Bekker, J. Dayton, A. Gilmour, I. Krainsky, M. Rose, R. Rameshan, D. File, G. Mearini
Secondary electron yields have been measured at NASA Lewis Research Center on diamond and diamond-like-carbon (DLC) films prepared at Auburn University. These results have been obtained as part of a study initiated by the Naval Surface Warfare Center. Secondary yields as high as 27 have been measured for the diamond films; the DLC films have maximum yields near 1.5. Secondary yields from the diamond films decline when they are subjected to continuous electron bombardment, but emission can be restored or enhanced if the surface is annealed in vacuum or exposed to hydrogen gas.<>
{"title":"Observations of secondary electron emission from diamond films","authors":"T. L. Bekker, J. Dayton, A. Gilmour, I. Krainsky, M. Rose, R. Rameshan, D. File, G. Mearini","doi":"10.1109/IEDM.1992.307513","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307513","url":null,"abstract":"Secondary electron yields have been measured at NASA Lewis Research Center on diamond and diamond-like-carbon (DLC) films prepared at Auburn University. These results have been obtained as part of a study initiated by the Naval Surface Warfare Center. Secondary yields as high as 27 have been measured for the diamond films; the DLC films have maximum yields near 1.5. Secondary yields from the diamond films decline when they are subjected to continuous electron bombardment, but emission can be restored or enhanced if the surface is annealed in vacuum or exposed to hydrogen gas.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126589318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307524
H. Kume, M. Kato, T. Adachi, T. Tanaka, T. Sasaki, T. Okazaki, N. Miyamoto, S. Saeki, Y. Ohji, M. Ushiyama, J. Yugami, T. Morimoto, T. Nishida
This paper describes a novel contactless memory cell technology for a 3V-only 64Mbit EEPROM with NOR structure. A new program/erase scheme using a Fowler-Nordheim tunneling mechanism is developed, resulting in a single 3V power supply operation. Scatter in "low-level" threshold voltage in a memory array, which seriously affects a read operation margin at a reduced V/sub c/c in the NOR structure, is also improved with this scheme. Based on a 0.4 mu m CMOS process, a small cell area of 1.28 mu m/sup 2/ is successfully realized by the contactless memory cell technology, demonstrating the 64Mbit integration capability.<>
{"title":"A 1.28 mu m/sup 2/ contactless memory cell technology for a 3 V-only 64 Mbit EEPROM","authors":"H. Kume, M. Kato, T. Adachi, T. Tanaka, T. Sasaki, T. Okazaki, N. Miyamoto, S. Saeki, Y. Ohji, M. Ushiyama, J. Yugami, T. Morimoto, T. Nishida","doi":"10.1109/IEDM.1992.307524","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307524","url":null,"abstract":"This paper describes a novel contactless memory cell technology for a 3V-only 64Mbit EEPROM with NOR structure. A new program/erase scheme using a Fowler-Nordheim tunneling mechanism is developed, resulting in a single 3V power supply operation. Scatter in \"low-level\" threshold voltage in a memory array, which seriously affects a read operation margin at a reduced V/sub c/c in the NOR structure, is also improved with this scheme. Based on a 0.4 mu m CMOS process, a small cell area of 1.28 mu m/sup 2/ is successfully realized by the contactless memory cell technology, demonstrating the 64Mbit integration capability.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"215 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122820851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307358
M. Yoshimaru, N. Inoue, M. Itoh, H. Kurogi, H. Tamura, N. Hirasita, F. Ichikawa, M. Ino
Si/sub 3/N/sub 4/ film deposited by LPCVD with in situ HF vapor cleaning has been applied to dielectric film of stacked capacitor. The composition of the Si/sub 3/N/sub 4/ film deposited on poly-Si electrode becomes stoichiometric. The film shows low leakage current and high electrical reliability. But it brings a new problem. Si/sub 3/N/sub 4/ film deposited using in situ HF vapor cleaning shows selective deposition on poly-Si electrode. The edge of poly-Si electrode is not covered by Si/sub 3/N/sub 4/ film. This problem is avoidable by carpeting Si/sub 3/N/sub 4/ film under poly-Si electrode. This process realizes further improvement of stacked capacitor dielectric film reliability.<>
{"title":"High quality ultra thin Si/sub 3/N/sub 4/ film selectively deposited on poly-Si electrode by LPCVD with in situ HF vapor cleaning","authors":"M. Yoshimaru, N. Inoue, M. Itoh, H. Kurogi, H. Tamura, N. Hirasita, F. Ichikawa, M. Ino","doi":"10.1109/IEDM.1992.307358","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307358","url":null,"abstract":"Si/sub 3/N/sub 4/ film deposited by LPCVD with in situ HF vapor cleaning has been applied to dielectric film of stacked capacitor. The composition of the Si/sub 3/N/sub 4/ film deposited on poly-Si electrode becomes stoichiometric. The film shows low leakage current and high electrical reliability. But it brings a new problem. Si/sub 3/N/sub 4/ film deposited using in situ HF vapor cleaning shows selective deposition on poly-Si electrode. The edge of poly-Si electrode is not covered by Si/sub 3/N/sub 4/ film. This problem is avoidable by carpeting Si/sub 3/N/sub 4/ film under poly-Si electrode. This process realizes further improvement of stacked capacitor dielectric film reliability.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121500481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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