Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791812
Antoine Perraudat, Alexandre Lima, S. Dauzére-Pérés, P. Vialletelle
This paper motivates the development of and presents a Decision Support System (DSS) for a critical Time Constraint Tunnel (TCT) in a High-Mix/Low-Volume (HMLV) 300mm wafer fab. The DSS downloads the status of the machines, their qualifications, the location of lots within and in front of the tunnel, and suggests release dates for lots of different critical technologies. The tunnel structure and the problem are described, together with the DSS and details on its implementation and industrial use.
{"title":"A decision support system for a critical time constraint tunnel","authors":"Antoine Perraudat, Alexandre Lima, S. Dauzére-Pérés, P. Vialletelle","doi":"10.1109/ASMC.2019.8791812","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791812","url":null,"abstract":"This paper motivates the development of and presents a Decision Support System (DSS) for a critical Time Constraint Tunnel (TCT) in a High-Mix/Low-Volume (HMLV) 300mm wafer fab. The DSS downloads the status of the machines, their qualifications, the location of lots within and in front of the tunnel, and suggests release dates for lots of different critical technologies. The tunnel structure and the problem are described, together with the DSS and details on its implementation and industrial use.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125953298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791746
Moshe Agam, A. Suwhanov, C. Gooch
Authors propose an alternative approach for deep substrate connection through buried layer using existing features in the fabrication process flow with simple and completely modular process integration. This is done by creating isolated conductive paths from the wafer surface to the substrate inside isolated pockets. By doing so, authors eliminate the need to connect directly from the backside of the wafer to the substrate and avoid added cost, as well as, the limitations of additional assembly process. In this approach, authors create isolated small pockets with Deep Trench Isolation (DTI) and add an implant to counter dope the buried layer inside these pockets. Technology Computer Aided Design (TCAD) is used to optimize the counter doping implant with consideration to the buried layer doping profile and the thermal drive of the entire process. Blind alignment is used for the new implant photo and is characterized to assure sufficient process margin.
{"title":"Alternative Approach for Substrate Connection Using Deep Trench Isolated Pockets","authors":"Moshe Agam, A. Suwhanov, C. Gooch","doi":"10.1109/ASMC.2019.8791746","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791746","url":null,"abstract":"Authors propose an alternative approach for deep substrate connection through buried layer using existing features in the fabrication process flow with simple and completely modular process integration. This is done by creating isolated conductive paths from the wafer surface to the substrate inside isolated pockets. By doing so, authors eliminate the need to connect directly from the backside of the wafer to the substrate and avoid added cost, as well as, the limitations of additional assembly process. In this approach, authors create isolated small pockets with Deep Trench Isolation (DTI) and add an implant to counter dope the buried layer inside these pockets. Technology Computer Aided Design (TCAD) is used to optimize the counter doping implant with consideration to the buried layer doping profile and the thermal drive of the entire process. Blind alignment is used for the new implant photo and is characterized to assure sufficient process margin.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130616326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791816
S. Pancharatnam, J. Wynne, Willie Muchrison, Y. Sulehria
The growth rate of titanium nitride (TiN) film is compared between preventive maintenance (PM) rounds showing differences in starting deposition rate after chamber coats and the number of coats required to return to optimal deposition rate. It is important to reach the constant deposition rate for process stability, and it is hypothesized that the self-limiting nature of atomic layer deposition (ALD) and surface conditions of the chamber parts exposed to the TiN film are the driving factors for the change in growth of the TiN film. Surface characterization of key chamber parts are analyzed and correlated to TiN film deposition rate.
{"title":"Effect of chamber surface coat on TiN film growth","authors":"S. Pancharatnam, J. Wynne, Willie Muchrison, Y. Sulehria","doi":"10.1109/ASMC.2019.8791816","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791816","url":null,"abstract":"The growth rate of titanium nitride (TiN) film is compared between preventive maintenance (PM) rounds showing differences in starting deposition rate after chamber coats and the number of coats required to return to optimal deposition rate. It is important to reach the constant deposition rate for process stability, and it is hypothesized that the self-limiting nature of atomic layer deposition (ALD) and surface conditions of the chamber parts exposed to the TiN film are the driving factors for the change in growth of the TiN film. Surface characterization of key chamber parts are analyzed and correlated to TiN film deposition rate.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124557123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791789
Taher Kagalwala, P. Timoney, Ron Fiege, Jason Emans, Timothy Hughes, Alexander Elia, A. Vaid, Susan Emans, Benny Vilge, Marjorie Cheng, Charles Kang, Darren Zingerman, Kevin Drayton, Naren Yellai, M. Sendelbach
In semiconductor manufacturing, the time it takes for wafers to process through the line is of utmost importance. Any delay in the processing of these wafers is very costly to the foundry and the end customer. Cycle time is one of the key metrics that any customer looks for in a foundry to ensure that their products are delivered on schedule. To improve overall cycle time, every equipment fleet needs to consistently and efficiently process wafers. In this paper, we will demonstrate sustainable improvements to key manufacturing metrics on Nova OCD fleet. The key metrics discussed are lot holds, recipe FTR (First-Time Right), fleet availability and fleet matching. Areas of improvement were analyzed, based on which an improvement strategy was developed and executed for each of the metrics. Weekly tracking of the respective metrics showed that the action plan was successful and sustainable. Similar approach could be applied to any metrology fleet to further improve manufacturing metrics.
{"title":"Improving Metrology Fleet KPIs for Advanced Foundry Manufacturing","authors":"Taher Kagalwala, P. Timoney, Ron Fiege, Jason Emans, Timothy Hughes, Alexander Elia, A. Vaid, Susan Emans, Benny Vilge, Marjorie Cheng, Charles Kang, Darren Zingerman, Kevin Drayton, Naren Yellai, M. Sendelbach","doi":"10.1109/ASMC.2019.8791789","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791789","url":null,"abstract":"In semiconductor manufacturing, the time it takes for wafers to process through the line is of utmost importance. Any delay in the processing of these wafers is very costly to the foundry and the end customer. Cycle time is one of the key metrics that any customer looks for in a foundry to ensure that their products are delivered on schedule. To improve overall cycle time, every equipment fleet needs to consistently and efficiently process wafers. In this paper, we will demonstrate sustainable improvements to key manufacturing metrics on Nova OCD fleet. The key metrics discussed are lot holds, recipe FTR (First-Time Right), fleet availability and fleet matching. Areas of improvement were analyzed, based on which an improvement strategy was developed and executed for each of the metrics. Weekly tracking of the respective metrics showed that the action plan was successful and sustainable. Similar approach could be applied to any metrology fleet to further improve manufacturing metrics.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127850588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791804
F. Baumann, Brian Popielarski, Yinggang Lu
We show how a CD-TEM (Critical Dimension- Transmission Electron Microscope) can be used to acquire EDS (Energy Dispersive X-ray Spectroscopy) tomograms, which allow chemical mapping in 3D for most elements in the sample. This is achieved by developing a recipe using ordinary commands also used in CD-TEM programming.
{"title":"Extension of CD-TEM towards EDS Tomography","authors":"F. Baumann, Brian Popielarski, Yinggang Lu","doi":"10.1109/ASMC.2019.8791804","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791804","url":null,"abstract":"We show how a CD-TEM (Critical Dimension- Transmission Electron Microscope) can be used to acquire EDS (Energy Dispersive X-ray Spectroscopy) tomograms, which allow chemical mapping in 3D for most elements in the sample. This is achieved by developing a recipe using ordinary commands also used in CD-TEM programming.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127910016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791792
J. Trujillo-Sevilla, J. Ramos-Rodríguez, J. Gaudestad
We present a new wafer metrology technique, Wave Front Phase Imaging (WFPI), for high speed measurement of wafer geometry including shape, flatness, nanotopography and even sub nm features found in roughness. WFPI acquires data of the entire wafer using a single image snapshot that provides depth data for every single pixel. The number of topography data points for the entire wafer will be proportional to the number of pixels in the image sensor. Sub nanometer depth resolution is achieved by using 2 cameras with optics that image the entire wafer, with the exact same field of view, at different conjugation planes. Monochromatic uncoherent light is illuminating the wafer and lateral resolution is determined by the lenses used for a specific field of view and the number of pixels offered by the image sensor. We show that WFPI can see warp and bow on a 2 inch wafer in addition to clearly resolving polishing artifacts in the roughness regime with dimensions well below the wavelength of the light.
{"title":"Wave Front Phase Imaging of Wafer Warpage : Advanced new metrology technique for blank incoming wafers","authors":"J. Trujillo-Sevilla, J. Ramos-Rodríguez, J. Gaudestad","doi":"10.1109/ASMC.2019.8791792","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791792","url":null,"abstract":"We present a new wafer metrology technique, Wave Front Phase Imaging (WFPI), for high speed measurement of wafer geometry including shape, flatness, nanotopography and even sub nm features found in roughness. WFPI acquires data of the entire wafer using a single image snapshot that provides depth data for every single pixel. The number of topography data points for the entire wafer will be proportional to the number of pixels in the image sensor. Sub nanometer depth resolution is achieved by using 2 cameras with optics that image the entire wafer, with the exact same field of view, at different conjugation planes. Monochromatic uncoherent light is illuminating the wafer and lateral resolution is determined by the lenses used for a specific field of view and the number of pixels offered by the image sensor. We show that WFPI can see warp and bow on a 2 inch wafer in addition to clearly resolving polishing artifacts in the roughness regime with dimensions well below the wavelength of the light.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115561202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791797
Shiladitya Chakravorty, Atirek Wribhu
Throughput of certain fast processing tool sets in a semiconductor Fab is sometimes constrained by limitations of FOUP delivery system. The delivery system not being able to keep up with the tools result in a certain throughput loss. This throughput loss can be mitigated by staging the WIP close to tools. However, WIP staging has its limitations. This study presents a methodology to overcome these limitations by staging the WIP just in time for dispatching.
{"title":"Throughput Optimization of Fast Processing Tools Using a Dispatching Algorithm","authors":"Shiladitya Chakravorty, Atirek Wribhu","doi":"10.1109/ASMC.2019.8791797","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791797","url":null,"abstract":"Throughput of certain fast processing tool sets in a semiconductor Fab is sometimes constrained by limitations of FOUP delivery system. The delivery system not being able to keep up with the tools result in a certain throughput loss. This throughput loss can be mitigated by staging the WIP close to tools. However, WIP staging has its limitations. This study presents a methodology to overcome these limitations by staging the WIP just in time for dispatching.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"44 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116644764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791802
C. Beitia, M. Abdel sater, M. Cordeau, S. Godny, S. Petitgrand, D. Alliata
Surface nanotopography is important for different key advanced process steps (CMP, Bonding, Epitaxy…). However, its characterization needs data at all scales from wafer to devices. In addition in today advanced processes, roughness and deterministic topography can be of the same order impacting signal/noise ratio. No single measurement is able to measure all scales and it is crucial to develop methodologies to combine data from different instruments. This will allow to optimize control plan by using the appropriate tool at a particular scale. Optical profiler and AFM measurements are well suited to cover all if not an important range of topography scales. The study compares results from both instrument and give a methodology to identify optimal scale for them. First benefits and limitations of both technologies will be discussed in terms of resolution/throughput. In a second step and overview of most used parameters characterization with its advantage and disadvantage will be presented. Finally, data comparison will be discussed in the frame of an alternative method which it is believed to get a clearer way to address such measurements.
{"title":"Optical profilometry and AFM measurements comparison on low amplitude deterministic surfaces","authors":"C. Beitia, M. Abdel sater, M. Cordeau, S. Godny, S. Petitgrand, D. Alliata","doi":"10.1109/ASMC.2019.8791802","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791802","url":null,"abstract":"Surface nanotopography is important for different key advanced process steps (CMP, Bonding, Epitaxy…). However, its characterization needs data at all scales from wafer to devices. In addition in today advanced processes, roughness and deterministic topography can be of the same order impacting signal/noise ratio. No single measurement is able to measure all scales and it is crucial to develop methodologies to combine data from different instruments. This will allow to optimize control plan by using the appropriate tool at a particular scale. Optical profiler and AFM measurements are well suited to cover all if not an important range of topography scales. The study compares results from both instrument and give a methodology to identify optimal scale for them. First benefits and limitations of both technologies will be discussed in terms of resolution/throughput. In a second step and overview of most used parameters characterization with its advantage and disadvantage will be presented. Finally, data comparison will be discussed in the frame of an alternative method which it is believed to get a clearer way to address such measurements.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130404621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791831
J. Ayala, Joshual Bell, K. Nummy, Fen Guan, Shuren Hu
The insatiable demand for digital information has led to the introduction and increasing adaptation of Silicon Photonics in digital communications to replace the much slower copper wires wherever possible. While most of today’s Silicon Photonics solutions are being manufactured using hybrid (no CMOS devices) integration, there is an increasing need to offer full integrated solutions (CMOS and Photonics) to improve system level performance and drive overall costs down. In this paper we’ll describe the challenges and innovative solutions used to develop and ultimately integrate a high performance Germanium (Ge) photodiode (PD) into a 90nm CMOS compatible process flow to provide a full monolithic Silicon Photonics solution.
{"title":"Integrating a high performance Germanium photodiode into a CMOS compatible flow for a full monolithic Silicon Photonics solution","authors":"J. Ayala, Joshual Bell, K. Nummy, Fen Guan, Shuren Hu","doi":"10.1109/ASMC.2019.8791831","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791831","url":null,"abstract":"The insatiable demand for digital information has led to the introduction and increasing adaptation of Silicon Photonics in digital communications to replace the much slower copper wires wherever possible. While most of today’s Silicon Photonics solutions are being manufactured using hybrid (no CMOS devices) integration, there is an increasing need to offer full integrated solutions (CMOS and Photonics) to improve system level performance and drive overall costs down. In this paper we’ll describe the challenges and innovative solutions used to develop and ultimately integrate a high performance Germanium (Ge) photodiode (PD) into a 90nm CMOS compatible process flow to provide a full monolithic Silicon Photonics solution.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117188816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791754
Satyajit Shinde, Lawrence Mbonu, H. Ali, Jea Sung Park, Xiao Chen
Minimal wafer loss is the goal of companies particularly in the cut throat semi-conductor industry. Unwanted moisture on the wafer surface at front end of the line can lead to defects in subsequent process steps. Typically, wafer surface exposed to moisture such as high humidity conditions can lead to wafer surface contamination. The moisture effect is addressed at a step which is after the initial processing steps thus minimizing the addition of any new steps affecting cycle time and cost of additional processing. Pre-clean, pad oxide and pad nitride are the typical initial steps of most of the technology nodes in semiconductor industry. Most of the work is done on wafer surface prior to introduction in the production line. This project focuses on addressing it at pad nitride step after the wafer is already processed in pre clean and pad oxide. Initially paper looks at the failure mode on incoming wafer surface, then methodology to eliminate or mitigate the incoming impact and finally optimize the step conditions for minimal impact.
{"title":"Novel Method to Address Wafer Surface Condition","authors":"Satyajit Shinde, Lawrence Mbonu, H. Ali, Jea Sung Park, Xiao Chen","doi":"10.1109/ASMC.2019.8791754","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791754","url":null,"abstract":"Minimal wafer loss is the goal of companies particularly in the cut throat semi-conductor industry. Unwanted moisture on the wafer surface at front end of the line can lead to defects in subsequent process steps. Typically, wafer surface exposed to moisture such as high humidity conditions can lead to wafer surface contamination. The moisture effect is addressed at a step which is after the initial processing steps thus minimizing the addition of any new steps affecting cycle time and cost of additional processing. Pre-clean, pad oxide and pad nitride are the typical initial steps of most of the technology nodes in semiconductor industry. Most of the work is done on wafer surface prior to introduction in the production line. This project focuses on addressing it at pad nitride step after the wafer is already processed in pre clean and pad oxide. Initially paper looks at the failure mode on incoming wafer surface, then methodology to eliminate or mitigate the incoming impact and finally optimize the step conditions for minimal impact.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126366203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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