Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962803
Kai-Chi Chen, H. Li, Che-Hao Shih, Wen-Bin Chen, Shu-Chen Huang
Copolymerization of PBZ precursors with epoxies forms network structures with high crosslinking densities, potentially improving the thermal and mechanical properties. In this study, we copolymerized the siloxane-imide-containing benzoxazine BZ-A6 was with siloxane-epoxy GT-1000. Analyses using differential scanning calorimetry and Fourier transform infrared spectroscopy revealed that the copolymers were formed at a relatively low curing temperature of 150 °C. The siloxane benzoxazine/epoxy mixture exhibited high thermal stability, with a high char yield of 44.6% and a high decomposition temperature of 364.9 °C. Moreover, during UV exposure tests, the water contact angle of the BZ-A6/GT-1000 copolymer was more stable than that of the conventional bisphenol A-type benzoxazine-epoxy Ba/DGEBA, suggesting that our new benzoxazine/epoxy mixture would be more suitable for applications requiring hydrophobic materials that are UV resistant. The low curing temperature and good temperature- and UV-resistance of this siloxane benzoxazine/epoxy mixture should make it widely applicable, such as IC package materials (film type encapsulant, paste encapsulant) or weather resistance application.
{"title":"A new thermosetting resin prepared from a siloxane-containing benzoxazine and epoxy resin","authors":"Kai-Chi Chen, H. Li, Che-Hao Shih, Wen-Bin Chen, Shu-Chen Huang","doi":"10.1109/ESTC.2014.6962803","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962803","url":null,"abstract":"Copolymerization of PBZ precursors with epoxies forms network structures with high crosslinking densities, potentially improving the thermal and mechanical properties. In this study, we copolymerized the siloxane-imide-containing benzoxazine BZ-A6 was with siloxane-epoxy GT-1000. Analyses using differential scanning calorimetry and Fourier transform infrared spectroscopy revealed that the copolymers were formed at a relatively low curing temperature of 150 °C. The siloxane benzoxazine/epoxy mixture exhibited high thermal stability, with a high char yield of 44.6% and a high decomposition temperature of 364.9 °C. Moreover, during UV exposure tests, the water contact angle of the BZ-A6/GT-1000 copolymer was more stable than that of the conventional bisphenol A-type benzoxazine-epoxy Ba/DGEBA, suggesting that our new benzoxazine/epoxy mixture would be more suitable for applications requiring hydrophobic materials that are UV resistant. The low curing temperature and good temperature- and UV-resistance of this siloxane benzoxazine/epoxy mixture should make it widely applicable, such as IC package materials (film type encapsulant, paste encapsulant) or weather resistance application.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126258613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962733
L. Brusberg, D. Manessis, M. Neitz, Beatrice Schild, H. Schroder, T. Tekin, K. Lang
The goal of our research is the development of a single-mode electro-optical circuit board, the single-mode board-to-board pluggable connector and the single-mode chip-to-board coupling interface to silicon photonic devices. In this paper, the single-mode glass waveguide process is presented based on thermal silver ion-exchange for fabrication of low loss glass waveguide panels that will be developed for embedding as core layer of such printed circuit board. The single-mode glass waveguides (SM-WGs) were fabricated on 150 mm wafer size for characterization of different embedding scenarios. In the best case the measured propagation loss before and after lamination is below 0.1 dB/cm (λ=1550 nm). A suitable glass waveguide layer and embedding process was developed that can be applied for single-mode electro-optical circuit board fabrication.
{"title":"Development of an electro-optical circuit board technology with embedded single-mode glass waveguide layer","authors":"L. Brusberg, D. Manessis, M. Neitz, Beatrice Schild, H. Schroder, T. Tekin, K. Lang","doi":"10.1109/ESTC.2014.6962733","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962733","url":null,"abstract":"The goal of our research is the development of a single-mode electro-optical circuit board, the single-mode board-to-board pluggable connector and the single-mode chip-to-board coupling interface to silicon photonic devices. In this paper, the single-mode glass waveguide process is presented based on thermal silver ion-exchange for fabrication of low loss glass waveguide panels that will be developed for embedding as core layer of such printed circuit board. The single-mode glass waveguides (SM-WGs) were fabricated on 150 mm wafer size for characterization of different embedding scenarios. In the best case the measured propagation loss before and after lamination is below 0.1 dB/cm (λ=1550 nm). A suitable glass waveguide layer and embedding process was developed that can be applied for single-mode electro-optical circuit board fabrication.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"222 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114004528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962840
Z. Wang, F. Jiang, W. Zhang
In 3D IC packaging, through silicon via (TSV) technology is being considered as a promising technology, enabling massive and short interconnections between stacked chips, increasing performance and data bandwidth, and reducing signal delay and the power consumption. Currently, dry etch process plays an important role in TSV fabrication. TSVs with diameters ranging from one hundred to ten micrometers are mainly fabricated by deep reactive ion etching (DRIE) technology. Bosch process is used for DRIE process for producing high-aspect ratio TSVs and non-Bosch process is used for TSV reveal process. In Bosch process, the primary steps are silicon isotropic etching and wall passivation in sequential cycles. SF6 is widely used as the main etching gas for the high density of F+ radicals; C4F8 is used in wall passivation as it polymerizes to deposits on walls to form an etch barrier that is sufficiently impervious to side scattered F+ ions but not to direct ions at the bottom of the via. Wall scalloping occurs primarily near the top of the via where scattered ions have wide trajectories and less at greater depths where ion trajectories are more restricted. After completion of the via-middle TSV integration and front-side wafer processing, the wafer is temporarily bonded onto a carrier wafer which could be glass or silicon. Then Si from the backside of the wafer was removed to make contact with the bottom of the TSVs by a mechanical grind followed by a reveal etch, which is a key step for the successful implementation of TSV. The via reveal was required to maintain acceptably low total thickness variation (TTV) to allow subsequent stacking steps.
{"title":"Si dry etching for TSV formation and backside reveal","authors":"Z. Wang, F. Jiang, W. Zhang","doi":"10.1109/ESTC.2014.6962840","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962840","url":null,"abstract":"In 3D IC packaging, through silicon via (TSV) technology is being considered as a promising technology, enabling massive and short interconnections between stacked chips, increasing performance and data bandwidth, and reducing signal delay and the power consumption. Currently, dry etch process plays an important role in TSV fabrication. TSVs with diameters ranging from one hundred to ten micrometers are mainly fabricated by deep reactive ion etching (DRIE) technology. Bosch process is used for DRIE process for producing high-aspect ratio TSVs and non-Bosch process is used for TSV reveal process. In Bosch process, the primary steps are silicon isotropic etching and wall passivation in sequential cycles. SF6 is widely used as the main etching gas for the high density of F+ radicals; C4F8 is used in wall passivation as it polymerizes to deposits on walls to form an etch barrier that is sufficiently impervious to side scattered F+ ions but not to direct ions at the bottom of the via. Wall scalloping occurs primarily near the top of the via where scattered ions have wide trajectories and less at greater depths where ion trajectories are more restricted. After completion of the via-middle TSV integration and front-side wafer processing, the wafer is temporarily bonded onto a carrier wafer which could be glass or silicon. Then Si from the backside of the wafer was removed to make contact with the bottom of the TSVs by a mechanical grind followed by a reveal etch, which is a key step for the successful implementation of TSV. The via reveal was required to maintain acceptably low total thickness variation (TTV) to allow subsequent stacking steps.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114847718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962713
J. Lo, S. Lee, Xungao Guo, Huishan Zhao
Phosphor converted LED is commonly used as the white light source in solid state luminaires. Among the packaging processes involved, phosphor deposition is a critical step, which controls the overall optical performance of LEDs. There are several phosphor deposition methods, among which disperse dispensing and conformal coating methods are widely used. In these two methods, phosphor materials are applied directly on top of the LED chip. The phosphor materials are heated up by the LED chip during the operation. The behavior of phosphor materials highly depends on their temperature. The emission efficiency decreases as temperature increases. High phosphor temperature may also introduce reliability problems. The situation can be improved by adopting a remote phosphor method. Some high power LEDs packages utilize silicone lens to increase the light extraction efficiency. It is difficult to apply a remote phosphor layer on the convex surface using a regular dispensing process. In this paper, an innovative multilayer remote phosphor deposition method is proposed for the packages with silicone lens. Phosphor slurry was dispensed directly on the silicone lens with steps. The slurry flowed and spread on the dome, and stopped when it reached the edge of the step. The unique step feature stopped the phosphor slurry from overflowing. A package with multilayer remote phosphor layer was fabricated. The phosphor material in each layer was different. This method provides a simple and flexible platform for adopting different types of phosphor materials in one package, and hence to achieve the designed optical performance.
{"title":"Multilayer dispensing of remote phosphor for LED wafer level packaging with pre-formed silicone lens","authors":"J. Lo, S. Lee, Xungao Guo, Huishan Zhao","doi":"10.1109/ESTC.2014.6962713","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962713","url":null,"abstract":"Phosphor converted LED is commonly used as the white light source in solid state luminaires. Among the packaging processes involved, phosphor deposition is a critical step, which controls the overall optical performance of LEDs. There are several phosphor deposition methods, among which disperse dispensing and conformal coating methods are widely used. In these two methods, phosphor materials are applied directly on top of the LED chip. The phosphor materials are heated up by the LED chip during the operation. The behavior of phosphor materials highly depends on their temperature. The emission efficiency decreases as temperature increases. High phosphor temperature may also introduce reliability problems. The situation can be improved by adopting a remote phosphor method. Some high power LEDs packages utilize silicone lens to increase the light extraction efficiency. It is difficult to apply a remote phosphor layer on the convex surface using a regular dispensing process. In this paper, an innovative multilayer remote phosphor deposition method is proposed for the packages with silicone lens. Phosphor slurry was dispensed directly on the silicone lens with steps. The slurry flowed and spread on the dome, and stopped when it reached the edge of the step. The unique step feature stopped the phosphor slurry from overflowing. A package with multilayer remote phosphor layer was fabricated. The phosphor material in each layer was different. This method provides a simple and flexible platform for adopting different types of phosphor materials in one package, and hence to achieve the designed optical performance.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114924077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962824
Wookyu Lee, Hyunmo Koo, Junfeng Sun, Yunchang Choi, Gyoujin Cho
R2R gravure with two printing units with the overlay printing registration accuracy of ±20 μm is introduced to fabricate 20 × 20 TFTs backplane on 150 m of PET web. The resultants of fully printed TFT backplanes were characterized based on the concept to extract the scalability for manufacturing wall paper like sensor sheets. In this gravure system, silver nanoparticle based conductive ink, BaTiO3 based dielectric ink and single walled carbon nanotube based semiconducting ink were used for printing 20 × 20 TFT backplanes on 100 m of PET web. Rheological properties were optimized with the consideration of printing reliability and electrical properties of resulting TFTs. Mobility, transconductance, threshold voltage, and on-off current ratio of 20 × 20 printed TFT backplanes were analyzed for extracting the parameters to define the scalability factors for practical applications.
{"title":"Fully roll-to-roll gravure printed carbon nanotube based flexible thin film transistor backplane on 100 m of poly(ethyleneterephtalate) (PET) web","authors":"Wookyu Lee, Hyunmo Koo, Junfeng Sun, Yunchang Choi, Gyoujin Cho","doi":"10.1109/ESTC.2014.6962824","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962824","url":null,"abstract":"R2R gravure with two printing units with the overlay printing registration accuracy of ±20 μm is introduced to fabricate 20 × 20 TFTs backplane on 150 m of PET web. The resultants of fully printed TFT backplanes were characterized based on the concept to extract the scalability for manufacturing wall paper like sensor sheets. In this gravure system, silver nanoparticle based conductive ink, BaTiO3 based dielectric ink and single walled carbon nanotube based semiconducting ink were used for printing 20 × 20 TFT backplanes on 100 m of PET web. Rheological properties were optimized with the consideration of printing reliability and electrical properties of resulting TFTs. Mobility, transconductance, threshold voltage, and on-off current ratio of 20 × 20 printed TFT backplanes were analyzed for extracting the parameters to define the scalability factors for practical applications.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123483175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962735
T. Zoller, Ricardo Ehrenpfordt, A. Gavrikov, J. Nurnus, H. Kuck
This paper focuses on packaging of thin film thermoelectric generators (TEG) for energy harvesting applications in sensor nodes for the internet of things (IoT). The TEGs have to be robust against mechanical stress caused by the assembly and packaging process steps and the mismatch of the coefficients of thermal expansion of the used materials. In this work, the mechanical stability of TEGs was evaluated by using a shear force test apparatus and a four line bending test. Furthermore the influence of underfill and stress decoupling thermal adhesives on the mechanical performance was investigated. It could be shown that underfill between the two substrates improves the shear force stability of the investigated thermoelectric generators. During mechanical tests the internal electrical resistance of the modules was monitored. It was observed, that the electrical shutdown coincides with the mechanical shutdown of the generator. By using selected thermal adhesives with and without underfill a sufficient robustness of the thermoelectric generator against typical warpage as known from a standard molded land grid array (LGA) sensor package was achieved.
{"title":"Packaging of thin film thermoelectric generators for autonomous sensor nodes","authors":"T. Zoller, Ricardo Ehrenpfordt, A. Gavrikov, J. Nurnus, H. Kuck","doi":"10.1109/ESTC.2014.6962735","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962735","url":null,"abstract":"This paper focuses on packaging of thin film thermoelectric generators (TEG) for energy harvesting applications in sensor nodes for the internet of things (IoT). The TEGs have to be robust against mechanical stress caused by the assembly and packaging process steps and the mismatch of the coefficients of thermal expansion of the used materials. In this work, the mechanical stability of TEGs was evaluated by using a shear force test apparatus and a four line bending test. Furthermore the influence of underfill and stress decoupling thermal adhesives on the mechanical performance was investigated. It could be shown that underfill between the two substrates improves the shear force stability of the investigated thermoelectric generators. During mechanical tests the internal electrical resistance of the modules was monitored. It was observed, that the electrical shutdown coincides with the mechanical shutdown of the generator. By using selected thermal adhesives with and without underfill a sufficient robustness of the thermoelectric generator against typical warpage as known from a standard molded land grid array (LGA) sensor package was achieved.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"13 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128867296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962758
H. Albrecht, J. Strogies
The main trends in consumer electronics are increasing product performances and costs reduction. These trends lead to an ongoing integration on package level which leads to a decreasing size of the solder contacts. This goes along with a higher sensibility to thermal-mechanical stress and the immanent void formation due to electromigration (EM) effects in interfaces and bulk materials like solder fillets or solder balls Following the Flip Chip-Technology in terms of Chip Size Packages or other miniaturized components, the size of solder bump interconnects have been significantly reduced with the development of high-density packaging, and therefore the evaluation of the electromigration behavior in solder bumps is significantly required. The paper proposes evaluation trials to test the electromigration resistance of different Pb-free solders, also with special additions to minimize material transport phenomena at interfaces and in the bulk (SnAgCu, SnAg+, SnBi+, SnAgBiSb+. SnAgBiIn+). Miniaturized interconnects with sufficient current density are under investigation to cause electromigration as phenomena concerning the diffusion of metallic atoms induced by high density electron flow and Joule heating, that can create local defects in terms of voids, etc. With the rapid downsizing of interconnections, the electromigration-resistant solder material and interfaces becomes more interest. In addition to that, for power electronic applications the acceptable current density must be compared with the design orientated constructional parameter in terms of back side metallizations of the die, bump or ball interconnects and the Cu width and thickness of wiring solutions in the package and the surrounding area. Results will be presented to discuss the risk of EM and solutions to stabilize interfaces. The electromigration effects are also under investigation for extended power electronics applications under the influence of Cu trace dimensions, electrical and thermal interfaces, current density applied, higher operating temperatures and metallizations in the vertical layer stack of power modules.
{"title":"Investigations studying the electromigration phenomena in interconnects","authors":"H. Albrecht, J. Strogies","doi":"10.1109/ESTC.2014.6962758","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962758","url":null,"abstract":"The main trends in consumer electronics are increasing product performances and costs reduction. These trends lead to an ongoing integration on package level which leads to a decreasing size of the solder contacts. This goes along with a higher sensibility to thermal-mechanical stress and the immanent void formation due to electromigration (EM) effects in interfaces and bulk materials like solder fillets or solder balls Following the Flip Chip-Technology in terms of Chip Size Packages or other miniaturized components, the size of solder bump interconnects have been significantly reduced with the development of high-density packaging, and therefore the evaluation of the electromigration behavior in solder bumps is significantly required. The paper proposes evaluation trials to test the electromigration resistance of different Pb-free solders, also with special additions to minimize material transport phenomena at interfaces and in the bulk (SnAgCu, SnAg+, SnBi+, SnAgBiSb+. SnAgBiIn+). Miniaturized interconnects with sufficient current density are under investigation to cause electromigration as phenomena concerning the diffusion of metallic atoms induced by high density electron flow and Joule heating, that can create local defects in terms of voids, etc. With the rapid downsizing of interconnections, the electromigration-resistant solder material and interfaces becomes more interest. In addition to that, for power electronic applications the acceptable current density must be compared with the design orientated constructional parameter in terms of back side metallizations of the die, bump or ball interconnects and the Cu width and thickness of wiring solutions in the package and the surrounding area. Results will be presented to discuss the risk of EM and solutions to stabilize interfaces. The electromigration effects are also under investigation for extended power electronics applications under the influence of Cu trace dimensions, electrical and thermal interfaces, current density applied, higher operating temperatures and metallizations in the vertical layer stack of power modules.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129159887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962816
Huayu Sun, Y. Chan
In this study, 0.5 wt.% CNTs-doped solder paste, that prepared by mechanical stirring, was used to detect the redistribution phenomenon of nanoparticles in the solder ball. Some of nanoparticles seriously separated out with the outward flow of solder flux, making related quantitative experiments loss their accuracy. Some of nanoparticles seriously gathered in the solder ball, having negative effects on the solder joint and making the phenomenon of degradation of reinforcement become serious. To study the degradation phenomenon of nanoparticle reinforced solder joint, mechanical properties of Sn58Bi, Sn57.6Bi0.4Ag and doped Sn58Bi+0.4Ag were compared during aging. According to the result of ball shear test, the degradation of reinforcement was seriously happened in the doped Sn58Bi+0.4Ag solder joints. Caused by the gathered Ag3Sn IMCs, the doped Sn58Bi+0.4Ag solder joints lost its mechanical advantages after 100h aging, comparing with Sn58Bi and Sn57.6Bi0.4Ag solder joints.
{"title":"Drawbacks of the nanoparticle reinforced lead-free BGA solder joints","authors":"Huayu Sun, Y. Chan","doi":"10.1109/ESTC.2014.6962816","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962816","url":null,"abstract":"In this study, 0.5 wt.% CNTs-doped solder paste, that prepared by mechanical stirring, was used to detect the redistribution phenomenon of nanoparticles in the solder ball. Some of nanoparticles seriously separated out with the outward flow of solder flux, making related quantitative experiments loss their accuracy. Some of nanoparticles seriously gathered in the solder ball, having negative effects on the solder joint and making the phenomenon of degradation of reinforcement become serious. To study the degradation phenomenon of nanoparticle reinforced solder joint, mechanical properties of Sn58Bi, Sn57.6Bi0.4Ag and doped Sn58Bi+0.4Ag were compared during aging. According to the result of ball shear test, the degradation of reinforcement was seriously happened in the doped Sn58Bi+0.4Ag solder joints. Caused by the gathered Ag3Sn IMCs, the doped Sn58Bi+0.4Ag solder joints lost its mechanical advantages after 100h aging, comparing with Sn58Bi and Sn57.6Bi0.4Ag solder joints.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125427716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962855
K. Matsunaga, Min-Su Kim, H. Nishikawa, M. Saito, J. Mizuno
As the establishment of high-temperature lead-free solders and other interconnection technologies is an urgent priority in the electronics industry, a strong drive exists to find Pb-free alternatives for high-temperature bonding processes. We propose a no-solvent, no-flux solid-state bonding technique that uses a nanoporous sheet, a process we call nanoporous bonding (NPB). Nanoporous sheets can be made from binary alloys by selective dissolution of one element. In this study, Au nanoporous sheets were fabricated by dealloying a Au-Ag binary alloy with nitric acid. The effects of joining conditions on the shear strength of joints using this sheet were investigated. The joints bonded at 350 °C showed high shear strengths of above 20 MPa. It was found that joining using Au NPB was successfully achieved, and that NPB shows potential as a Pb-free interconnection material for high-temperature electronic applications.
{"title":"Relationship between bonding conditions and strength for joints using a Au nanoporous sheet","authors":"K. Matsunaga, Min-Su Kim, H. Nishikawa, M. Saito, J. Mizuno","doi":"10.1109/ESTC.2014.6962855","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962855","url":null,"abstract":"As the establishment of high-temperature lead-free solders and other interconnection technologies is an urgent priority in the electronics industry, a strong drive exists to find Pb-free alternatives for high-temperature bonding processes. We propose a no-solvent, no-flux solid-state bonding technique that uses a nanoporous sheet, a process we call nanoporous bonding (NPB). Nanoporous sheets can be made from binary alloys by selective dissolution of one element. In this study, Au nanoporous sheets were fabricated by dealloying a Au-Ag binary alloy with nitric acid. The effects of joining conditions on the shear strength of joints using this sheet were investigated. The joints bonded at 350 °C showed high shear strengths of above 20 MPa. It was found that joining using Au NPB was successfully achieved, and that NPB shows potential as a Pb-free interconnection material for high-temperature electronic applications.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124477587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962719
H. Lundén, T. Kumpulainen, Antti Matanen, J. Vihinen
Conventional glass bonding methods do not fill all the requirements set by the industry. A novel hermetic room temperature glass welding technology was investigated. The aim was to avoid additive materials and multistep manufacturing process as well as minimize the heat affect. However, a good quality hermetic, mechanically sound bond was desired. In this study, a temperature cycling test was performed to glass samples welded with this novel technology. Notable advantages of using the novel welding technology were discovered: resistance of rapid temperature changes, excellent mechanical properties, room temperature welding, and hermetic encapsulation can be achieved. Use of only one material ensures that no problems with different temperature coefficients will be appeared. As a result, a newly develop glass welding technology can offer solution for the novel challenges set by the industry.
{"title":"Novel glass welding technique for hermetic encapsulation","authors":"H. Lundén, T. Kumpulainen, Antti Matanen, J. Vihinen","doi":"10.1109/ESTC.2014.6962719","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962719","url":null,"abstract":"Conventional glass bonding methods do not fill all the requirements set by the industry. A novel hermetic room temperature glass welding technology was investigated. The aim was to avoid additive materials and multistep manufacturing process as well as minimize the heat affect. However, a good quality hermetic, mechanically sound bond was desired. In this study, a temperature cycling test was performed to glass samples welded with this novel technology. Notable advantages of using the novel welding technology were discovered: resistance of rapid temperature changes, excellent mechanical properties, room temperature welding, and hermetic encapsulation can be achieved. Use of only one material ensures that no problems with different temperature coefficients will be appeared. As a result, a newly develop glass welding technology can offer solution for the novel challenges set by the industry.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126187982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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