Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409731
E. Forsythe, Benjamin J. Leever, Mark Gordon, R. Vaia, D. Morton, M. Durstock, R. Woods
To date, there has been a strong consensus that U.S. flexible electronics technology and manufacturing efforts have demonstrated the potential for significant US-based job creation in small businesses to Fortune-500 companies. These jobs will impact across product supply chains, from raw materials production to retail sales of new devices. Flexible electronics is enabling a technology base that has the opportunity for the next high-tech manufacturing job creation. Early silicon CMOS manufacturing created high paying manufacturing jobs in US fabrication lines. Today, many of these jobs are moving to foreign Countries. Flexible electronics manufacturing approaches open the opportunity for innovative, low-cost fabrication techniques combining traditional US-strengths in plate-to-plate semiconductor manufacturing with roll-to-roll printing. Such approaches will enable mid-size companies to enter into manufacturing thereby broadening the job creation within the US. These innovative approaches to achieve the low-cost and high volume products will enable a US manufacturing dominance in an emerging Global industry. Future flexible electronics commercial and Defense Department applications include; wearable and medical sensors, structural monitoring devices, medical sensors, soft robotics, Internet of Things, and integrated array antennas on structures.
{"title":"Flexible electronics for commercial and defense applications","authors":"E. Forsythe, Benjamin J. Leever, Mark Gordon, R. Vaia, D. Morton, M. Durstock, R. Woods","doi":"10.1109/IEDM.2015.7409731","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409731","url":null,"abstract":"To date, there has been a strong consensus that U.S. flexible electronics technology and manufacturing efforts have demonstrated the potential for significant US-based job creation in small businesses to Fortune-500 companies. These jobs will impact across product supply chains, from raw materials production to retail sales of new devices. Flexible electronics is enabling a technology base that has the opportunity for the next high-tech manufacturing job creation. Early silicon CMOS manufacturing created high paying manufacturing jobs in US fabrication lines. Today, many of these jobs are moving to foreign Countries. Flexible electronics manufacturing approaches open the opportunity for innovative, low-cost fabrication techniques combining traditional US-strengths in plate-to-plate semiconductor manufacturing with roll-to-roll printing. Such approaches will enable mid-size companies to enter into manufacturing thereby broadening the job creation within the US. These innovative approaches to achieve the low-cost and high volume products will enable a US manufacturing dominance in an emerging Global industry. Future flexible electronics commercial and Defense Department applications include; wearable and medical sensors, structural monitoring devices, medical sensors, soft robotics, Internet of Things, and integrated array antennas on structures.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133120429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409788
Lingfei Wang, Song-ang Peng, Z. Zong, Ling Li, Wen Wang, Guangwei Xu, Nianduan Lu, Z. Ji, Zhi Jin, Ming Liu
For the first time, we present a continuous surface potential based physical compact model for GFET and benchmark our work against device measurements. This model is based on semi-classical Boltzmann transport and thermally activated transport theories, including both remote and short range scattering mechanisms. Therefore the model is temperature dependent. Meanwhile, we provide the corresponding method to extract the key physical parameters. Furthermore, the compact model is coded in Verilog-A, and can be implemented in vendor CAD tools. The model provides a physics-based consistent description of DC and AC device characteristics and enables accurate circuit-level performance estimation and RF circuit design of GFET.
{"title":"A new surface potential based physical compact model for GFET in RF applications","authors":"Lingfei Wang, Song-ang Peng, Z. Zong, Ling Li, Wen Wang, Guangwei Xu, Nianduan Lu, Z. Ji, Zhi Jin, Ming Liu","doi":"10.1109/IEDM.2015.7409788","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409788","url":null,"abstract":"For the first time, we present a continuous surface potential based physical compact model for GFET and benchmark our work against device measurements. This model is based on semi-classical Boltzmann transport and thermally activated transport theories, including both remote and short range scattering mechanisms. Therefore the model is temperature dependent. Meanwhile, we provide the corresponding method to extract the key physical parameters. Furthermore, the compact model is coded in Verilog-A, and can be implemented in vendor CAD tools. The model provides a physics-based consistent description of DC and AC device characteristics and enables accurate circuit-level performance estimation and RF circuit design of GFET.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"32 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116650835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409671
C. Y. Chen, A. Fantini, L. Goux, R. Degraeve, S. Clima, A. Redolfi, Guido Groeseneken, M. Jurczak
We investigate the impact of pulse programming conditions on data-retention of 40nm × 40nm TiNHfO2Hf RRAM devices, focusing on the failure of tail bits. We demonstrate that retention loss tail bit is not due to out diffusion of filament constituents but by low activation-energy (Ea~0.5eV) diffusing species, which are understood as metastable Oxygen (O)-ions in the neighborhood of the conductive-filament constriction. In order to minimize their impact, effective programming pathways are demonstrated, as the low-Ea population is better reduced by (i) using longer Write pulses rather than higher current-pulse amplitudes, and/or by (ii) using shorter reset pulse prior to Write set.
{"title":"Programming-conditions solutions towards suppression of retention tails of scaled oxide-based RRAM","authors":"C. Y. Chen, A. Fantini, L. Goux, R. Degraeve, S. Clima, A. Redolfi, Guido Groeseneken, M. Jurczak","doi":"10.1109/IEDM.2015.7409671","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409671","url":null,"abstract":"We investigate the impact of pulse programming conditions on data-retention of 40nm × 40nm TiNHfO2Hf RRAM devices, focusing on the failure of tail bits. We demonstrate that retention loss tail bit is not due to out diffusion of filament constituents but by low activation-energy (Ea~0.5eV) diffusing species, which are understood as metastable Oxygen (O)-ions in the neighborhood of the conductive-filament constriction. In order to minimize their impact, effective programming pathways are demonstrated, as the low-Ea population is better reduced by (i) using longer Write pulses rather than higher current-pulse amplitudes, and/or by (ii) using shorter reset pulse prior to Write set.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124990253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409761
J. Ida, Takayuki Mori, Yousuke Kuramoto, Takashi Horii, Takahiro Yoshida, Kazuma Takeda, H. Kasai, M. Okihara, Y. Arai
We propose and demonstrate a super steep Subthreshold Slope (SS) new type SOI FET with a PN-body tied structure. It has a symmetry source and drain (S/D) structure. The device shows a super steep SS (<;6mV/dec) over 3 decades of the drain current with an ultralow drain voltage down to 0.1V. It also shows a low leakage current (below 1pA/um), a good Id-Vd characteristic and a negligible hysteresis characteristic.
{"title":"Super steep subthreshold slope PN-body tied SOI FET with ultra low drain voltage down to 0.1V","authors":"J. Ida, Takayuki Mori, Yousuke Kuramoto, Takashi Horii, Takahiro Yoshida, Kazuma Takeda, H. Kasai, M. Okihara, Y. Arai","doi":"10.1109/IEDM.2015.7409761","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409761","url":null,"abstract":"We propose and demonstrate a super steep Subthreshold Slope (SS) new type SOI FET with a PN-body tied structure. It has a symmetry source and drain (S/D) structure. The device shows a super steep SS (<;6mV/dec) over 3 decades of the drain current with an ultralow drain voltage down to 0.1V. It also shows a low leakage current (below 1pA/um), a good Id-Vd characteristic and a negligible hysteresis characteristic.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125111848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409746
R. Aitken, V. Chandra, D. Pietromonaco
System-on-chip designs must take into account a large number of sources of variability in order to be manufacturable with suitable yield. Resilient design must begin with careful attention to these methods, but must also move beyond them. This paper looks at the need to consider dynamic aging variation for BTI effects as part of an overall resilient design methodology. Note that this aging tolerance will be needed even for fault tolerant approaches such as lockstep or triple-modular redundancy, because the aging process will occur in all copies of a design at roughly the same rate.
{"title":"Implications of variability on resilient design","authors":"R. Aitken, V. Chandra, D. Pietromonaco","doi":"10.1109/IEDM.2015.7409746","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409746","url":null,"abstract":"System-on-chip designs must take into account a large number of sources of variability in order to be manufacturable with suitable yield. Resilient design must begin with careful attention to these methods, but must also move beyond them. This paper looks at the need to consider dynamic aging variation for BTI effects as part of an overall resilient design methodology. Note that this aging tolerance will be needed even for fault tolerant approaches such as lockstep or triple-modular redundancy, because the aging process will occur in all copies of a design at roughly the same rate.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126143245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409777
H. Mulaosmanovic, S. Slesazeck, J. Ocker, M. Pešić, S. Muller, S. Flachowsky, J. Muller, P. Polakowski, J. Paul, S. Jansen, S. Kolodinski, C. Richter, S. Piontek, T. Schenk, A. Kersch, C. Kunneth, R. van Bentum, U. Schroder, T. Mikolajick
Recent discovery of ferroelectricity in HfO2 thin films paved the way for demonstration of ultra-scaled 28 nm Ferroelectric FETs (FeFET) as non-volatile memory (NVM) cells [1]. However, such small devices are inevitably sensible to the granularity of the polycrystalline gate oxide film. Here we report for the first time the evidence of single ferroelectric (FE) domain switching in such scaled devices. These properties are sensed in terms of abrupt threshold voltage (VT) shifts leading to stable intermediate VT levels. We emphasize that this feature enables multi-level cell (MLC) FeFETs and gives a new perspective on steep subthreshold devices based on ferroelectric HfO2.
{"title":"Evidence of single domain switching in hafnium oxide based FeFETs: Enabler for multi-level FeFET memory cells","authors":"H. Mulaosmanovic, S. Slesazeck, J. Ocker, M. Pešić, S. Muller, S. Flachowsky, J. Muller, P. Polakowski, J. Paul, S. Jansen, S. Kolodinski, C. Richter, S. Piontek, T. Schenk, A. Kersch, C. Kunneth, R. van Bentum, U. Schroder, T. Mikolajick","doi":"10.1109/IEDM.2015.7409777","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409777","url":null,"abstract":"Recent discovery of ferroelectricity in HfO2 thin films paved the way for demonstration of ultra-scaled 28 nm Ferroelectric FETs (FeFET) as non-volatile memory (NVM) cells [1]. However, such small devices are inevitably sensible to the granularity of the polycrystalline gate oxide film. Here we report for the first time the evidence of single ferroelectric (FE) domain switching in such scaled devices. These properties are sensed in terms of abrupt threshold voltage (VT) shifts leading to stable intermediate VT levels. We emphasize that this feature enables multi-level cell (MLC) FeFETs and gives a new perspective on steep subthreshold devices based on ferroelectric HfO2.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130096767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409827
Yiming Li, Han-Tung Chang, C. Lai, Pei-Jung Chao, Chieh-Yang Chen
In this work, process variation effect (PVE), work function fluctuation (WKF), and random dopant fluctuation (RDF) on 10-nm high-K/metal gate gate-all-around silicon nanowire MOSFET devices using full-quantum-mechanically validated and experimentally calibrated device simulation are studied. The small aspect ratio device has greater immunity of RDF, while suffers from PVE and WKF.
{"title":"Process variation effect, metal-gate work-function fluctuation and random dopant fluctuation of 10-nm gate-all-around silicon nanowire MOSFET devices","authors":"Yiming Li, Han-Tung Chang, C. Lai, Pei-Jung Chao, Chieh-Yang Chen","doi":"10.1109/IEDM.2015.7409827","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409827","url":null,"abstract":"In this work, process variation effect (PVE), work function fluctuation (WKF), and random dopant fluctuation (RDF) on 10-nm high-K/metal gate gate-all-around silicon nanowire MOSFET devices using full-quantum-mechanically validated and experimentally calibrated device simulation are studied. The small aspect ratio device has greater immunity of RDF, while suffers from PVE and WKF.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129298636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409668
S. Kim, T. J. Ha, S. Kim, Jae Yeon Lee, K. Kim, Jungho Shin, Yong Taek Park, S. P. Song, B. Kim, W. Kim, Jong Chul Lee, Hyun Sun Lee, Jong Hwang Song, E. Hwang, S. Cho, J. Ku, Jong Il Kim, Kyu Sung Kim, Jong-Hee Yoo, Hyo Jin Kim, Hoe Gwon Jung, Kee-jeung Lee, Suock Chung, Jong Kang, Jung Hoon Lee, H. Kim, S. Hong, G. Gibson, Yoocharn Jeon
In this paper, the authors report that 2x nm cross-point ReRAM with 1S1R structure has been successfully developed. Off-current at 1/2 Vsw of 1S1R is one of key factor for high-density ReRAM. NbO2 was chosen as a selector material and off-current and forming characteristics were improved by using stack engineering of top and bottom barriers as well as spacer materials. Finally array operation was characterized with the integration of selector and resistor materials.
{"title":"Improvement of characteristics of NbO2 selector and full integration of 4F2 2x-nm tech 1S1R ReRAM","authors":"S. Kim, T. J. Ha, S. Kim, Jae Yeon Lee, K. Kim, Jungho Shin, Yong Taek Park, S. P. Song, B. Kim, W. Kim, Jong Chul Lee, Hyun Sun Lee, Jong Hwang Song, E. Hwang, S. Cho, J. Ku, Jong Il Kim, Kyu Sung Kim, Jong-Hee Yoo, Hyo Jin Kim, Hoe Gwon Jung, Kee-jeung Lee, Suock Chung, Jong Kang, Jung Hoon Lee, H. Kim, S. Hong, G. Gibson, Yoocharn Jeon","doi":"10.1109/IEDM.2015.7409668","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409668","url":null,"abstract":"In this paper, the authors report that 2x nm cross-point ReRAM with 1S1R structure has been successfully developed. Off-current at 1/2 Vsw of 1S1R is one of key factor for high-density ReRAM. NbO2 was chosen as a selector material and off-current and forming characteristics were improved by using stack engineering of top and bottom barriers as well as spacer materials. Finally array operation was characterized with the integration of selector and resistor materials.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117218622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409703
Y. Morita, T. Maeda, H. Ota, W. Mizubayashi, S. O'Uchi, M. Masahara, T. Matsukawa, K. Endo
We have developed a novel wafer-scale uniform layer-by-layer etching technology based on the etching reaction of oxygen molecules with Ge surfaces. The advantages of this etching technology are as follows. (1) Layer-by-layer etching can be achieved, yielding an atomically flat step-terrace surface. (2) Because of the very small activation energy (<;0.1 eV) of the etching reaction, this technology is free from etch rate variation caused by temperature inhomogeneity over large wafers. (3) No plasma damage occurs as a result of O2 molecule reactions with anisotropic etching. These features are applicable to the fabrication of three-dimensional Ge channels.
{"title":"Novel wafer-scale uniform layer-by-layer etching technology for line edge roughness reduction and surface flattening of 3D Ge channels","authors":"Y. Morita, T. Maeda, H. Ota, W. Mizubayashi, S. O'Uchi, M. Masahara, T. Matsukawa, K. Endo","doi":"10.1109/IEDM.2015.7409703","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409703","url":null,"abstract":"We have developed a novel wafer-scale uniform layer-by-layer etching technology based on the etching reaction of oxygen molecules with Ge surfaces. The advantages of this etching technology are as follows. (1) Layer-by-layer etching can be achieved, yielding an atomically flat step-terrace surface. (2) Because of the very small activation energy (<;0.1 eV) of the etching reaction, this technology is free from etch rate variation caused by temperature inhomogeneity over large wafers. (3) No plasma damage occurs as a result of O2 molecule reactions with anisotropic etching. These features are applicable to the fabrication of three-dimensional Ge channels.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124477429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409824
Raseong Kim, U. Avci, I. Young
As MOSFET scaling continues [1], new n- and p-channel materials are being actively explored to deliver performance targets better than Si. In this paper, we present CMOS performance benchmarking results for Si, InAs, GaAs, and Ge nanowire (NW) n- and pMOSFETs with LG=13 nm (ITRS node of year 2018 [1-3]) based on atomistic quantum transport simulation [4] and including strain effects [5]. Uniaxial [6] tensile/compressive strain mostly increases nMOS/pMOS drive current and vice versa, but results may be different for low power (LP) operation because strain may also affect the tunneling leakage current. We also discuss the threshold voltage (Vth) sensitivity to strain, which may have an impact on the device variation. Finally, we compare current (I), capacitance (C), and energy (CV2) vs. delay (CV/I) trade-off (for gate or interconnect loading) across different n-channel (Si, InAs, GaAs, Ge) and p-channel (Si, Ge) materials considering extrinsic parasitic components (RSD, Cfringe) for different supply voltages (VDD's). We project that Ge CMOS (using <;110> NWs [7]) with source/drain (S/D) doping density (Nsd) optimized [8] depending on the operating condition (high performance (HP) or LP) may deliver the best drive current and CV2 vs. CV/I while it would also benefit from the homogeneous material integration. For low capacitance (low power consumption), III-V-Ge hybrid CMOS is most advantageous.
{"title":"CMOS performance benchmarking of Si, InAs, GaAs, and Ge nanowire n- and pMOSFETs with Lg=13 nm based on atomistic quantum transport simulation including strain effects","authors":"Raseong Kim, U. Avci, I. Young","doi":"10.1109/IEDM.2015.7409824","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409824","url":null,"abstract":"As MOSFET scaling continues [1], new n- and p-channel materials are being actively explored to deliver performance targets better than Si. In this paper, we present CMOS performance benchmarking results for Si, InAs, GaAs, and Ge nanowire (NW) n- and pMOSFETs with LG=13 nm (ITRS node of year 2018 [1-3]) based on atomistic quantum transport simulation [4] and including strain effects [5]. Uniaxial [6] tensile/compressive strain mostly increases nMOS/pMOS drive current and vice versa, but results may be different for low power (LP) operation because strain may also affect the tunneling leakage current. We also discuss the threshold voltage (Vth) sensitivity to strain, which may have an impact on the device variation. Finally, we compare current (I), capacitance (C), and energy (CV2) vs. delay (CV/I) trade-off (for gate or interconnect loading) across different n-channel (Si, InAs, GaAs, Ge) and p-channel (Si, Ge) materials considering extrinsic parasitic components (RSD, Cfringe) for different supply voltages (VDD's). We project that Ge CMOS (using <;110> NWs [7]) with source/drain (S/D) doping density (Nsd) optimized [8] depending on the operating condition (high performance (HP) or LP) may deliver the best drive current and CV2 vs. CV/I while it would also benefit from the homogeneous material integration. For low capacitance (low power consumption), III-V-Ge hybrid CMOS is most advantageous.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121359799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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