Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409773
L. Thomas, G. Jan, S. Le, Yuan-Jen Lee, Huanlong Liu, Jian Zhu, S. Serrano-Guisan, R. Tong, K. Pi, D. Shen, R. He, J. Haq, Z. Teng, R. Annapragada, V. Lam, Yu-Jen Wang, T. Zhong, T. Torng, P. Wang
Current understanding of thermal stability of perpendicular STT-MRAM based on device-level data suggests that the thermal stability factor A is almost independent of device diameter above ~30nm. Here we report that contrary to this conventional wisdom, chip-level data retention exhibits substantial size dependence for diameters between 55 and 100 nm. We show that the method widely used to measure A is inaccurate for devices larger than ~30 nm, leading to significant underestimation of the size dependence. We derive an improved model, allowing us to reconcile the size dependence of A measured at device and chip level.
{"title":"Solving the paradox of the inconsistent size dependence of thermal stability at device and chip-level in perpendicular STT-MRAM","authors":"L. Thomas, G. Jan, S. Le, Yuan-Jen Lee, Huanlong Liu, Jian Zhu, S. Serrano-Guisan, R. Tong, K. Pi, D. Shen, R. He, J. Haq, Z. Teng, R. Annapragada, V. Lam, Yu-Jen Wang, T. Zhong, T. Torng, P. Wang","doi":"10.1109/IEDM.2015.7409773","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409773","url":null,"abstract":"Current understanding of thermal stability of perpendicular STT-MRAM based on device-level data suggests that the thermal stability factor A is almost independent of device diameter above ~30nm. Here we report that contrary to this conventional wisdom, chip-level data retention exhibits substantial size dependence for diameters between 55 and 100 nm. We show that the method widely used to measure A is inaccurate for devices larger than ~30 nm, leading to significant underestimation of the size dependence. We derive an improved model, allowing us to reconcile the size dependence of A measured at device and chip level.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130944300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409709
D. Marcon, Y. Saripalli, S. Decoutere
In this work, three types of high-voltage buffer architectures for GaN-on-200mm-Si epitaxy are compared and discussed. Two device architectures, recessed gate MISHEMTs and p-GaN HEMTs technology, to obtain e-mode operation developed on these buffers are also discussed. Threshold voltage/output current tuning, threshold voltage stability and possible issues are highlighted. A possible device architecture that combines the best of the two approaches is proposed together with preliminary test results.
{"title":"200mm GaN-on-Si epitaxy and e-mode device technology","authors":"D. Marcon, Y. Saripalli, S. Decoutere","doi":"10.1109/IEDM.2015.7409709","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409709","url":null,"abstract":"In this work, three types of high-voltage buffer architectures for GaN-on-200mm-Si epitaxy are compared and discussed. Two device architectures, recessed gate MISHEMTs and p-GaN HEMTs technology, to obtain e-mode operation developed on these buffers are also discussed. Threshold voltage/output current tuning, threshold voltage stability and possible issues are highlighted. A possible device architecture that combines the best of the two approaches is proposed together with preliminary test results.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"260 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133465115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409655
J. Michailos, P. Coudrain, A. Farcy, N. Hotellier, S. Chéramy, S. Lhostis, E. Deloffre, Y. Sanchez, A. Jouve, F. Guyader, E. Saugier, V. Fiori, P. Vivet, M. Vinet, C. Fenouillet-Béranger, F. Casset, P. Batude, F. Breuf, Y. Henrion, B. Vianne, L. Collin, J. Colonna, L. Benaissa, L. Brunet, R. Prieto, R. Vélard, F. Ponthenier
From low density 3D integrations embedding Via Last Through Silicon Vias (TSV) to high densities hybrid bonding or 3D VSLI CoolCubeTM solutions, a multitude of new product opportunities is now envisioned. An overview of existing emerging 3D integrations is provided covering Image sensors, Photonics, MEMS, Wide I/O memories and Silicon Interposers for advanced logics. Associated key challenges and developments are highlighted focusing on 3D platform performance assessment.
{"title":"New challenges and opportunities for 3D integrations","authors":"J. Michailos, P. Coudrain, A. Farcy, N. Hotellier, S. Chéramy, S. Lhostis, E. Deloffre, Y. Sanchez, A. Jouve, F. Guyader, E. Saugier, V. Fiori, P. Vivet, M. Vinet, C. Fenouillet-Béranger, F. Casset, P. Batude, F. Breuf, Y. Henrion, B. Vianne, L. Collin, J. Colonna, L. Benaissa, L. Brunet, R. Prieto, R. Vélard, F. Ponthenier","doi":"10.1109/IEDM.2015.7409655","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409655","url":null,"abstract":"From low density 3D integrations embedding Via Last Through Silicon Vias (TSV) to high densities hybrid bonding or 3D VSLI CoolCubeTM solutions, a multitude of new product opportunities is now envisioned. An overview of existing emerging 3D integrations is provided covering Image sensors, Photonics, MEMS, Wide I/O memories and Silicon Interposers for advanced logics. Associated key challenges and developments are highlighted focusing on 3D platform performance assessment.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114514420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409662
Jin Wei, Sheng-gen Liu, Baikui Li, Xi Tang, Yunyou Lu, Cheng Liu, M. Hua, Zhaofu Zhang, Gaofei Tang, K. J. Chen
An enhancement-mode GaN double-channel MOS-HEMT (DC-MOS-HEMT) was fabricated on a double-channel heterostructure, which features a 1.5-nm AlN layer (AlN-ISL) inserted 6 nm below the conventional barrier/GaN hetero-interface, forming a lower channel at the interface between AlN-ISL and the underlying GaN. With the gate recess terminated at the upper GaN channel layer, a positive threshold voltage is obtained, while the lower channel retains its high 2DEG mobility as the heterojunction is preserved. The fabricated device delivers a small on-resistance, large current, high breakdown voltage, and sharp subthreshold swing. The large tolerance for gate recess depth is also confirmed by both simulation and experiment.
{"title":"Enhancement-mode GaN double-channel MOS-HEMT with low on-resistance and robust gate recess","authors":"Jin Wei, Sheng-gen Liu, Baikui Li, Xi Tang, Yunyou Lu, Cheng Liu, M. Hua, Zhaofu Zhang, Gaofei Tang, K. J. Chen","doi":"10.1109/IEDM.2015.7409662","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409662","url":null,"abstract":"An enhancement-mode GaN double-channel MOS-HEMT (DC-MOS-HEMT) was fabricated on a double-channel heterostructure, which features a 1.5-nm AlN layer (AlN-ISL) inserted 6 nm below the conventional barrier/GaN hetero-interface, forming a lower channel at the interface between AlN-ISL and the underlying GaN. With the gate recess terminated at the upper GaN channel layer, a positive threshold voltage is obtained, while the lower channel retains its high 2DEG mobility as the heterojunction is preserved. The fabricated device delivers a small on-resistance, large current, high breakdown voltage, and sharp subthreshold swing. The large tolerance for gate recess depth is also confirmed by both simulation and experiment.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114788038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Stacked grid structure is implemented into back-side illumination (BSI) image sensors and device performance for various grid design including dimension and height has been investigated. Simulated angular response shows less quantum efficiency (QE) degradation in large incident angle and SNR-10 has a ~10% improvement for devices with stacked grid structure.
{"title":"Optical performance study of BSI image sensor with stacked grid structure","authors":"Yun-Wei Cheng, T. Tsai, Chun-Hao Chou, Kuo-cheng Lee, Hsin-Chi Chen, Yung-Lung Hsu","doi":"10.1109/IEDM.2015.7409801","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409801","url":null,"abstract":"Stacked grid structure is implemented into back-side illumination (BSI) image sensors and device performance for various grid design including dimension and height has been investigated. Simulated angular response shows less quantum efficiency (QE) degradation in large incident angle and SNR-10 has a ~10% improvement for devices with stacked grid structure.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115049771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409621
M. B. Sky, N. Sosa, T. Masuda, W. Kim, S. Kim, A. Ray, R. Bruce, J. Gonsalves, Y. Zhu, K. Suu, C. Lam
We show, for the first time, a robust high aspect ratio (~4:1) confined PCM cell which utilizes a dense and highly reliable nano-crystalline-as-deposited ALD phase change material. The 33nm diameter pore structures were filled utilizing an in-situ metal nitride liner plus nano-crystalline ALD Ge-Sb-Te material. The tuned process for depositing and integrating the phase change material brings the programming endurance to beyond 2.8×1011. We demonstrate a fast programming speed of 80ns with 10x switching and, with the aid of simulation, show a path for these elements to create a high density PCM cell suitable for Storage Class Memory.
{"title":"Crystalline-as-deposited ALD phase change material confined PCM cell for high density storage class memory","authors":"M. B. Sky, N. Sosa, T. Masuda, W. Kim, S. Kim, A. Ray, R. Bruce, J. Gonsalves, Y. Zhu, K. Suu, C. Lam","doi":"10.1109/IEDM.2015.7409621","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409621","url":null,"abstract":"We show, for the first time, a robust high aspect ratio (~4:1) confined PCM cell which utilizes a dense and highly reliable nano-crystalline-as-deposited ALD phase change material. The 33nm diameter pore structures were filled utilizing an in-situ metal nitride liner plus nano-crystalline ALD Ge-Sb-Te material. The tuned process for depositing and integrating the phase change material brings the programming endurance to beyond 2.8×1011. We demonstrate a fast programming speed of 80ns with 10x switching and, with the aid of simulation, show a path for these elements to create a high density PCM cell suitable for Storage Class Memory.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128405349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409666
P. Cappelletti
For over 40 years, the evolution of Non Volatile Memories has been mostly based on the floating gate MOS transistor. We have successfully succeeded in scaling this wonderful device below 20nm but we are now approaching the limit. It is time for disruptive innovations, either integrating the same basic device in a vertical structure or moving to totally different device concepts. This paper analyzes the different alternatives in relation to their areas of application.
{"title":"Non volatile memory evolution and revolution","authors":"P. Cappelletti","doi":"10.1109/IEDM.2015.7409666","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409666","url":null,"abstract":"For over 40 years, the evolution of Non Volatile Memories has been mostly based on the floating gate MOS transistor. We have successfully succeeded in scaling this wonderful device below 20nm but we are now approaching the limit. It is time for disruptive innovations, either integrating the same basic device in a vertical structure or moving to totally different device concepts. This paper analyzes the different alternatives in relation to their areas of application.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134153392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409665
K. Nomoto, Z. Hu, B. Song, M. Zhu, M. Qi, R. Yan, V. Protasenko, E. Imhoff, J. Kuo, N. Kaneda, T. Mishima, T. Nakamura, D. Jena, H. Xing
We report GaN p-n diodes on free-standing GaN substrates: a record high Baliga's figure-of-merit (V<;sub>B<;/sub><;sup>2<;/sup>/ Ron) of 12.8 GW/cm<;sup>2<;/sup> is achieved with a 32 μm drift layer and a diode diameter of 107 μm exhibiting a BV > 3.4 kV and a R<;sub>on<;/sub> <; 1 mΩ-cm<;sup>2<;/sup>. The leakage current density is low: 10<;sup>-3<;/sup> - 10<;sup>-4<;/sup> A/cm<;sup>2<;/sup> at 3 kV. A record low ideality factor of 1.1-1.3 is signature of high GaN quality. These are among the best-reported GaN p-n diodes.
{"title":"GaN-on-GaN p-n power diodes with 3.48 kV and 0.95 mΩ-cm2: A record high figure-of-merit of 12.8 GW/cm2","authors":"K. Nomoto, Z. Hu, B. Song, M. Zhu, M. Qi, R. Yan, V. Protasenko, E. Imhoff, J. Kuo, N. Kaneda, T. Mishima, T. Nakamura, D. Jena, H. Xing","doi":"10.1109/IEDM.2015.7409665","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409665","url":null,"abstract":"We report GaN p-n diodes on free-standing GaN substrates: a record high Baliga's figure-of-merit (V<;sub>B<;/sub><;sup>2<;/sup>/ Ron) of 12.8 GW/cm<;sup>2<;/sup> is achieved with a 32 μm drift layer and a diode diameter of 107 μm exhibiting a BV > 3.4 kV and a R<;sub>on<;/sub> <; 1 mΩ-cm<;sup>2<;/sup>. The leakage current density is low: 10<;sup>-3<;/sup> - 10<;sup>-4<;/sup> A/cm<;sup>2<;/sup> at 3 kV. A record low ideality factor of 1.1-1.3 is signature of high GaN quality. These are among the best-reported GaN p-n diodes.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132985784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409798
Y. Takemoto, K. Kobayashi, M. Tsukimura, N. Takazawa, H. Kato, S. Suzuki, J. Aoki, T. Kondo, H. Saito, Y. Gomi, S. Matsuda, Y. Tadaki
We demonstrated multiband imaging with a multi-storied photodiode CMOS image sensor (CIS), which comprises two individually functioning layered devices that achieve optimized images in different substrates bonded by 3D technology. The sensor is able to capture a wide variety of multiband images, which is not limited to conventional visible RGB (Red Green Blue) images taken with a Bayer filter or to invisible infrared (IR) images, at the same time without any color or image degradation even with an extra IR light source. Its wide range sensitivity enables us to select the specific narrow band light wave with specific optical filter in addition to visible RGB images. This wide selection of specific wavelengths of light is useful for specific applications like medical systems to identify pathological lesions and also enables additional functions on the same sensor to make such systems smarter, smaller, and cheaper than the conventional combination of IR imaging sensors with RGB image ones. A wide selection of multiband images is also possible with our device by modifying the top semiconductor layer thickness or changing the characteristics of a color filter on the top substrate to cover a wide range of application needs.
{"title":"Multi-storied photodiode CMOS image sensor for multiband imaging with 3D technology","authors":"Y. Takemoto, K. Kobayashi, M. Tsukimura, N. Takazawa, H. Kato, S. Suzuki, J. Aoki, T. Kondo, H. Saito, Y. Gomi, S. Matsuda, Y. Tadaki","doi":"10.1109/IEDM.2015.7409798","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409798","url":null,"abstract":"We demonstrated multiband imaging with a multi-storied photodiode CMOS image sensor (CIS), which comprises two individually functioning layered devices that achieve optimized images in different substrates bonded by 3D technology. The sensor is able to capture a wide variety of multiband images, which is not limited to conventional visible RGB (Red Green Blue) images taken with a Bayer filter or to invisible infrared (IR) images, at the same time without any color or image degradation even with an extra IR light source. Its wide range sensitivity enables us to select the specific narrow band light wave with specific optical filter in addition to visible RGB images. This wide selection of specific wavelengths of light is useful for specific applications like medical systems to identify pathological lesions and also enables additional functions on the same sensor to make such systems smarter, smaller, and cheaper than the conventional combination of IR imaging sensors with RGB image ones. A wide selection of multiband images is also possible with our device by modifying the top semiconductor layer thickness or changing the characteristics of a color filter on the top substrate to cover a wide range of application needs.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134162637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We have first manufactured Complementary Tunnel-FETs (C-TFETs) in standard 12-inch CMOS foundry. With abrupt tunnel junction consideration for improved TFET performance, technology of monolithically integrating C-TFET with CMOS is developed. Planar Si C-TFET inverter is also demonstrated, indicating a new electrical isolation requirement between neighboring devices for practical C-TFET integration on bulk substrate. For high-volume production, the variability of C-TFETs are experimentally investigated, demonstrating an intrinsic trade-off between performance enhancement and variability suppression induced by dominant variation source in traditional TFETs, which is mainly impacted by the band-to-band tunneling generation area. By new TFET device design, improved performance and variability simultaneously are experimentally achieved, and circuit-level implementation shows significant operation speed enhancement (up to 93%) and energy reduction (by 66%) at VDD of 0.4V, as well as remarkably suppressed variation, indicating its great potential for ultralow-power applications.
{"title":"First foundry platform of complementary tunnel-FETs in CMOS baseline technology for ultralow-power IoT applications: Manufacturability, variability and technology roadmap","authors":"Qianqian Huang, Rundong Jia, Cheng Chen, Hao Zhu, Lingyi Guo, Junyao Wang, Jiaxin Wang, Chunlei Wu, Runsheng Wang, Weihai Bu, Jin Kang, Wenbo Wang, Hanming Wu, Shiuh-Wuu Lee, Yangyuan Wang, Ru Huang","doi":"10.1109/IEDM.2015.7409756","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409756","url":null,"abstract":"We have first manufactured Complementary Tunnel-FETs (C-TFETs) in standard 12-inch CMOS foundry. With abrupt tunnel junction consideration for improved TFET performance, technology of monolithically integrating C-TFET with CMOS is developed. Planar Si C-TFET inverter is also demonstrated, indicating a new electrical isolation requirement between neighboring devices for practical C-TFET integration on bulk substrate. For high-volume production, the variability of C-TFETs are experimentally investigated, demonstrating an intrinsic trade-off between performance enhancement and variability suppression induced by dominant variation source in traditional TFETs, which is mainly impacted by the band-to-band tunneling generation area. By new TFET device design, improved performance and variability simultaneously are experimentally achieved, and circuit-level implementation shows significant operation speed enhancement (up to 93%) and energy reduction (by 66%) at VDD of 0.4V, as well as remarkably suppressed variation, indicating its great potential for ultralow-power applications.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134328861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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