Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306789
Hongliang Lv, Yimen Zhang, Yu-Ming Zhang
A numerical model for 4H-SiC Schottky barrier diode is presented in this paper and the breakdown performances are achieved. The influence of the edge termination extension on the breakdown characteristic is calculated and analyzed in detail.
{"title":"The simulation breakdown characteristic of 4H-SiC SBD with edge termination extension","authors":"Hongliang Lv, Yimen Zhang, Yu-Ming Zhang","doi":"10.1109/IWJT.2004.1306789","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306789","url":null,"abstract":"A numerical model for 4H-SiC Schottky barrier diode is presented in this paper and the breakdown performances are achieved. The influence of the edge termination extension on the breakdown characteristic is calculated and analyzed in detail.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125633686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306780
Hu Hengsheng, Chen Shoumian
In this paper, two approaches to form CoSi/sub 2/, Co/Ti and Co/TiN, were studied. It was found that reactive Ti was helpful to reduce the influence of surface condition with non-uniform monosilicide formation even without surface cleaning. However, Co/TiN without surface cleaning could not form monosilicide at all. When the thermal budget of RTP2 is too high, the disilicide on Boron doped polylines was easier to be degraded, both poor Rsh distribution and rougher surface were seen. Based on stable R/sub sh/ and junction leakage performance of patterned wafers, it can be said that the Co salicide process is successfully being developed for 0.18/spl mu/m technology, and has the capability to be extended to at least 0.15/spl mu/m technology.
{"title":"Study of Co silicidation process for 0.18/0.15/spl mu/m CMOS technology","authors":"Hu Hengsheng, Chen Shoumian","doi":"10.1109/IWJT.2004.1306780","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306780","url":null,"abstract":"In this paper, two approaches to form CoSi/sub 2/, Co/Ti and Co/TiN, were studied. It was found that reactive Ti was helpful to reduce the influence of surface condition with non-uniform monosilicide formation even without surface cleaning. However, Co/TiN without surface cleaning could not form monosilicide at all. When the thermal budget of RTP2 is too high, the disilicide on Boron doped polylines was easier to be degraded, both poor Rsh distribution and rougher surface were seen. Based on stable R/sub sh/ and junction leakage performance of patterned wafers, it can be said that the Co salicide process is successfully being developed for 0.18/spl mu/m technology, and has the capability to be extended to at least 0.15/spl mu/m technology.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115933786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306778
Yu-Long Jiang, A. Agarwal, G. Ru, X. Qu, Bingzong Li
The dopant (arsenic and boron) redistribution induced by Ni silicidation at 300/spl deg/C is investigated by cross-section transmission electron microscopy and secondary ion mass spectroscopy. The dopant segregation at silicide/Si interface is observed. Also a high concentration dopant peak near silicide surface is revealed and attributed to void layer formation due to Kirkendall voiding effect and volume reduction after silicidation. The re-segregation during the conversion from Ni/sub 2/Si to NiSi contributes an extra boron peak in the middle region of the formed silicide film on P+/N Si.
{"title":"Dopant redistribution induced by Ni silicidation at 300/spl deg/C","authors":"Yu-Long Jiang, A. Agarwal, G. Ru, X. Qu, Bingzong Li","doi":"10.1109/IWJT.2004.1306778","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306778","url":null,"abstract":"The dopant (arsenic and boron) redistribution induced by Ni silicidation at 300/spl deg/C is investigated by cross-section transmission electron microscopy and secondary ion mass spectroscopy. The dopant segregation at silicide/Si interface is observed. Also a high concentration dopant peak near silicide surface is revealed and attributed to void layer formation due to Kirkendall voiding effect and volume reduction after silicidation. The re-segregation during the conversion from Ni/sub 2/Si to NiSi contributes an extra boron peak in the middle region of the formed silicide film on P+/N Si.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"3 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133113386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306857
Z. Di, Miao Zhang, Weili Liu, S. Luo, Z. An, Zhengxuan Zhang, Zhitang Song, Chenglu Lin
Zr/sub 0.6/Al/sub 0.4/O/sub 1.8/ dielectric films were deposited directly on strained SiGe substrate at room temperature by ultra-high vacuum electron-beam evaporation (UHV-EBE) and then annealed in N/sub 2/ under various temperatures. X-ray diffraction (XRD) reveals that the onset crystallization temperature of the Zr/sub 0.6/Al/sub 0.4/O/sub 1.8/ film is about 900/spl deg/C, 400/spl deg/C higher than that of pure ZrO/sub 2/. The amorphous Zr/sub 0.6/Al/sub 0.4/O/sub 1.8/ film with a physical thickness of /spl sim/ 12 nm and an amorphous interfacial layer (IL) with a physical thickness of /spl sim/3 nm have been observed by high-resolution transmission electron microscopy (HRTEM). In addition, it is demonstrated there is no undesirable amorphous phase separation during annealing at temperatures below and equal to 800/spl deg/C in the Zr/sub 0.6/Al/sub 0.4/O/sub 1.8/ film. X-ray photoelectron spectroscopy (XPS) reveals that zirconium and aluminum are both in the fully oxidation states.
{"title":"The thermal stability of zirconium aluminate high-k film on strained SiGe layer","authors":"Z. Di, Miao Zhang, Weili Liu, S. Luo, Z. An, Zhengxuan Zhang, Zhitang Song, Chenglu Lin","doi":"10.1109/IWJT.2004.1306857","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306857","url":null,"abstract":"Zr/sub 0.6/Al/sub 0.4/O/sub 1.8/ dielectric films were deposited directly on strained SiGe substrate at room temperature by ultra-high vacuum electron-beam evaporation (UHV-EBE) and then annealed in N/sub 2/ under various temperatures. X-ray diffraction (XRD) reveals that the onset crystallization temperature of the Zr/sub 0.6/Al/sub 0.4/O/sub 1.8/ film is about 900/spl deg/C, 400/spl deg/C higher than that of pure ZrO/sub 2/. The amorphous Zr/sub 0.6/Al/sub 0.4/O/sub 1.8/ film with a physical thickness of /spl sim/ 12 nm and an amorphous interfacial layer (IL) with a physical thickness of /spl sim/3 nm have been observed by high-resolution transmission electron microscopy (HRTEM). In addition, it is demonstrated there is no undesirable amorphous phase separation during annealing at temperatures below and equal to 800/spl deg/C in the Zr/sub 0.6/Al/sub 0.4/O/sub 1.8/ film. X-ray photoelectron spectroscopy (XPS) reveals that zirconium and aluminum are both in the fully oxidation states.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115360668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306744
S. Deleonibus
Historically, innovations have been possible because of the strong association of devices and materials research. The demand for low voltage, low power and high performance are the great challenges for engineering of sub 50 nm gate length CMOS devices. We point out the main issues to address in order to investigate and push the limits of CMOS technology. The alternative architectures allowing to increase devices drivability and reduce power are reviewed. Among the materials options to be integrated, HiK gate dielectric and metal gate are among the most strategic options to consider for power consumption and low supply voltage management. New architectures and options are reviewed through the issues to address in gate/channel and substrate, gate dielectric as well as source and drain engineering. It will be very difficult to compete with CMOS logic because of the low series resistance required to obtain high performance. By introducing new materials, Si based CMOS will be scaled beyond the ITRS as the future System-on-Chip Platform integrating new disruptive devices. Functionality of devices in the range of 5 nm channel length has been demonstrated showing that CMOS technology could still be used in the future if we manage to implement new materials and device architecture options.
{"title":"The nanoelectronic CMOS era: silicon meets the other materials on the roadmap","authors":"S. Deleonibus","doi":"10.1109/IWJT.2004.1306744","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306744","url":null,"abstract":"Historically, innovations have been possible because of the strong association of devices and materials research. The demand for low voltage, low power and high performance are the great challenges for engineering of sub 50 nm gate length CMOS devices. We point out the main issues to address in order to investigate and push the limits of CMOS technology. The alternative architectures allowing to increase devices drivability and reduce power are reviewed. Among the materials options to be integrated, HiK gate dielectric and metal gate are among the most strategic options to consider for power consumption and low supply voltage management. New architectures and options are reviewed through the issues to address in gate/channel and substrate, gate dielectric as well as source and drain engineering. It will be very difficult to compete with CMOS logic because of the low series resistance required to obtain high performance. By introducing new materials, Si based CMOS will be scaled beyond the ITRS as the future System-on-Chip Platform integrating new disruptive devices. Functionality of devices in the range of 5 nm channel length has been demonstrated showing that CMOS technology could still be used in the future if we manage to implement new materials and device architecture options.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114730805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306776
J. Yun, Soon-Young Oh, H. Ji, Bin-Feng Huang, Y. Park, Jin-Suk Wang, H. Lee
A novel NiSi technology is proposed to improve the thermal stability and to suppress the abnormal oxidation of NiSi, which occurs especially on the As-doped substrate. The dependence of Nickel-Silicide property on the source/drain dopants has also been characterized. Although there is minimal dependence of NiSi on the dopants right after the silicide formation, NiSi is strongly dependent on the source/drain dopants when high temperature post silicidation furnace annealing is applied. BF/sub 2/-doped source/drain shows much superior thermally robust characteristics than As-doped source/drain mainly due to the abnormal oxidation of As-doped substrate after the furnace annealing. A novel Ti/Ni/TiN structure with fluorine ion implantation (F I/I in short) showed the great improvement of the thermal stability as well as the suppression of the abnormal oxidation especially on the As-doped source/drain.
{"title":"Novel NiSi technology utilizing Ti/Ni/TiN structure and fluorine implantation for thermal stability improvement by suppression of abnormal oxidation","authors":"J. Yun, Soon-Young Oh, H. Ji, Bin-Feng Huang, Y. Park, Jin-Suk Wang, H. Lee","doi":"10.1109/IWJT.2004.1306776","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306776","url":null,"abstract":"A novel NiSi technology is proposed to improve the thermal stability and to suppress the abnormal oxidation of NiSi, which occurs especially on the As-doped substrate. The dependence of Nickel-Silicide property on the source/drain dopants has also been characterized. Although there is minimal dependence of NiSi on the dopants right after the silicide formation, NiSi is strongly dependent on the source/drain dopants when high temperature post silicidation furnace annealing is applied. BF/sub 2/-doped source/drain shows much superior thermally robust characteristics than As-doped source/drain mainly due to the abnormal oxidation of As-doped substrate after the furnace annealing. A novel Ti/Ni/TiN structure with fluorine ion implantation (F I/I in short) showed the great improvement of the thermal stability as well as the suppression of the abnormal oxidation especially on the As-doped source/drain.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130179054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306787
Xue Li, Yong Kang, Xiangyang Li, H. Gong, Haxiong Fang
Non-intentionally-doped wurtzite GaN epitaxial layers used in this study were grown on (0001) sapphire by metal organic chemical vapour deposition technique. Ti/Al(24nm/90nm) contacts were deposited by ion beam sputtering. Effect of rapid thermal annealing on Ti/Al-GaN contacts was investigated by I-V measurements and AES depth profiles. Surface morphologies were characterized by AFM. Schottky barrier height and specific contact resistivity decreased at first and then increased as annealing temperature increased. The lowest specific contact resistivity was obtained at 600/spl deg/C, i.e.3.04 /spl times/ 10/sup -4//spl Omega//spl middot/cm/sup 2/. However, the ideality factors increased with increase of annealing temperatures. Auger depth profile analysis showed that Ti had diffused into annealed GaN samples, a heavily n-doped layer formed at Ti/GaN interface. The tunneling current mechanism played a role in increase of ideality factors after annealing. The changes of surface morphologies at different annealing temperatures were characterized by AFM. The root mean square roughness of the as-grown sample was 2.9/spl Aring/. After 600/spl deg/C annealing, the root mean square roughness increased to 41.5/spl Aring/. These results showed that thermal annealing-induced changes near the surface region of contacts were significant. The thermal stability of contacts needs further study. Ohmic contacts formed at 600/spl deg/C are due to lower barrier height and tunneling current transport.
{"title":"Effect of rapid thermal annealing on Ti/Al-GaN contacts","authors":"Xue Li, Yong Kang, Xiangyang Li, H. Gong, Haxiong Fang","doi":"10.1109/IWJT.2004.1306787","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306787","url":null,"abstract":"Non-intentionally-doped wurtzite GaN epitaxial layers used in this study were grown on (0001) sapphire by metal organic chemical vapour deposition technique. Ti/Al(24nm/90nm) contacts were deposited by ion beam sputtering. Effect of rapid thermal annealing on Ti/Al-GaN contacts was investigated by I-V measurements and AES depth profiles. Surface morphologies were characterized by AFM. Schottky barrier height and specific contact resistivity decreased at first and then increased as annealing temperature increased. The lowest specific contact resistivity was obtained at 600/spl deg/C, i.e.3.04 /spl times/ 10/sup -4//spl Omega//spl middot/cm/sup 2/. However, the ideality factors increased with increase of annealing temperatures. Auger depth profile analysis showed that Ti had diffused into annealed GaN samples, a heavily n-doped layer formed at Ti/GaN interface. The tunneling current mechanism played a role in increase of ideality factors after annealing. The changes of surface morphologies at different annealing temperatures were characterized by AFM. The root mean square roughness of the as-grown sample was 2.9/spl Aring/. After 600/spl deg/C annealing, the root mean square roughness increased to 41.5/spl Aring/. These results showed that thermal annealing-induced changes near the surface region of contacts were significant. The thermal stability of contacts needs further study. Ohmic contacts formed at 600/spl deg/C are due to lower barrier height and tunneling current transport.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130747002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306790
H. Chuang, C. Uang, S. Cheng, Chun-Yuan Chen, P. Lai, C. Kao, Y. Tsai, W. Hsu, Wen-Chau Liu
An interesting InGaP/InGaAs heterostructure field-effect transistor utilizing dual /spl delta/-doped quantum wells as double channels is studied and demonstrated. The employed dual /spl delta/-doped quantum wells and InGaP layer provide good carrier confinement and Schottky behavior, respectively. Good device performances including higher turn-on and breakdown voltages, high and linear transconductance and RF properties are obtained. For a 1 /spl times/ 100 /spl mu/m device, turn-on voltage of 1.74 V, maximum output current of 499 mA/mm, and maximum transconductance of 162 mS/mm with 303 mA/mm broad operation regime are obtained. The microwave properties of f/sub T/ and f/sub max/ are 16 and 32.3 GHz, respectively. Furthermore, even the device is operated at higher temperature regime (>400K), insignificant degradations of DC and RF performances are observed.
{"title":"InGaP/InGaAs dual-channel transistor","authors":"H. Chuang, C. Uang, S. Cheng, Chun-Yuan Chen, P. Lai, C. Kao, Y. Tsai, W. Hsu, Wen-Chau Liu","doi":"10.1109/IWJT.2004.1306790","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306790","url":null,"abstract":"An interesting InGaP/InGaAs heterostructure field-effect transistor utilizing dual /spl delta/-doped quantum wells as double channels is studied and demonstrated. The employed dual /spl delta/-doped quantum wells and InGaP layer provide good carrier confinement and Schottky behavior, respectively. Good device performances including higher turn-on and breakdown voltages, high and linear transconductance and RF properties are obtained. For a 1 /spl times/ 100 /spl mu/m device, turn-on voltage of 1.74 V, maximum output current of 499 mA/mm, and maximum transconductance of 162 mS/mm with 303 mA/mm broad operation regime are obtained. The microwave properties of f/sub T/ and f/sub max/ are 16 and 32.3 GHz, respectively. Furthermore, even the device is operated at higher temperature regime (>400K), insignificant degradations of DC and RF performances are observed.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121544382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306753
Y. Kawasaki, K. Tokunaga, K. Horita, K. Mitsuda, A. Yamaguchi, A. Ueno, A. Teratani, T. Katayama, K. Hayami, A. Togawa, Y. Ohno, M. Yoneda
We looked for possible mechanical damage to the gate electrodes during implantation in high-current implanter of batch type and we found that there was damage in gate electrodes with a length of 60 nm to 85 nm, which is caused by collision with particles. It was confirmed that the damage is dependent on spin speed, gate direction and existence of photo resist.
{"title":"The collapse of gate electrode in high-current implanter of batch type","authors":"Y. Kawasaki, K. Tokunaga, K. Horita, K. Mitsuda, A. Yamaguchi, A. Ueno, A. Teratani, T. Katayama, K. Hayami, A. Togawa, Y. Ohno, M. Yoneda","doi":"10.1109/IWJT.2004.1306753","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306753","url":null,"abstract":"We looked for possible mechanical damage to the gate electrodes during implantation in high-current implanter of batch type and we found that there was damage in gate electrodes with a length of 60 nm to 85 nm, which is caused by collision with particles. It was confirmed that the damage is dependent on spin speed, gate direction and existence of photo resist.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124981926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306855
Qing Lin, M. Zhu, Yan-jun Wu, Xinyun Xie, Zhengxuan Zhang, Cheng-lu Lin
We present a simulation-based approach for characterizing hot-carrier degradation in SOI MOSFETs, which includes models for hot-carrier injection, carrier transport, and carrier trapping in the gate oxide. This approach clearly illustrates the physical mechanisms responsible for hot-carrier degradation in SOI MOSFETs. To suppress the hot-carrier effect, we have also proposed the SOI LDDMOSFET structure and the simulation results have been compared with each other.
{"title":"Numerical simulation of hot-carrier degradation in SOI MOSFETs","authors":"Qing Lin, M. Zhu, Yan-jun Wu, Xinyun Xie, Zhengxuan Zhang, Cheng-lu Lin","doi":"10.1109/IWJT.2004.1306855","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306855","url":null,"abstract":"We present a simulation-based approach for characterizing hot-carrier degradation in SOI MOSFETs, which includes models for hot-carrier injection, carrier transport, and carrier trapping in the gate oxide. This approach clearly illustrates the physical mechanisms responsible for hot-carrier degradation in SOI MOSFETs. To suppress the hot-carrier effect, we have also proposed the SOI LDDMOSFET structure and the simulation results have been compared with each other.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125234444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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