Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114547
Huaxing Tang, Ting-Pu Tai, Wu-Tung Cheng, B. Benware, F. Hapke
The semiconductor industry is encountering an increasing number of front-end-of-line defects in the advanced FinFET technology nodes due to extremely small feature size and complex manufacturing processes required for FinFET transistors. Traditional delay diagnosis algorithm has a limited support for cell internal timing related failures based on transition delay faults, and tends to provide a large suspect list. It cannot provide the precise defect location inside the cell that is necessary for effective physical failure analysis and statistical yield learning. In this work, we present a new cell-aware delay diagnosis algorithm, based on accurate delay fault models derived by analog simulation, which can pinpoint the defect location within a cell for various timing related cell internal defects. Preliminary results for real silicon failures show that significant diagnosis resolution improvement can be achieved by the proposed method.
{"title":"Diagnosing timing related cell internal defects for FinFET technology","authors":"Huaxing Tang, Ting-Pu Tai, Wu-Tung Cheng, B. Benware, F. Hapke","doi":"10.1109/VLSI-DAT.2015.7114547","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114547","url":null,"abstract":"The semiconductor industry is encountering an increasing number of front-end-of-line defects in the advanced FinFET technology nodes due to extremely small feature size and complex manufacturing processes required for FinFET transistors. Traditional delay diagnosis algorithm has a limited support for cell internal timing related failures based on transition delay faults, and tends to provide a large suspect list. It cannot provide the precise defect location inside the cell that is necessary for effective physical failure analysis and statistical yield learning. In this work, we present a new cell-aware delay diagnosis algorithm, based on accurate delay fault models derived by analog simulation, which can pinpoint the defect location within a cell for various timing related cell internal defects. Preliminary results for real silicon failures show that significant diagnosis resolution improvement can be achieved by the proposed method.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133701127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114494
Yi-Hang Chen, Yang-Wen Chen, Juinn-Dar Huang
The power dissipation has become a crucial issue for most electronic circuit and system designs nowadays when fabrication processes exploit even deeper submicron technology. In particular, leakage power is becoming a dominant source of power consumption. In recent years, the reconfigurable single-electron transistor (SET) array has been proposed as an emerging circuit design style for continuing Moore's Law due to its ultra-low power consumption. Several automated synthesis techniques for area minimization have been developed for the reconfigurable SET array in the past few years. Nevertheless, most of those existing methods focus on variable and product term reordering during SET mapping. In fact, minimizing the number of product terms can greatly reduce the area as well, which has not been well addressed before. In this paper, we propose a dynamic shifting based variable ordering algorithm that can minimize the number of disjoint sum-of-product terms extracted from the given ROBDD. Experimental results show that the proposed method can achieve an area reduction of up to 49% as compared to current state-of-the-art techniques.
{"title":"ROBDD-based area minimization synthesis for reconfigurable single-electron transistor arrays","authors":"Yi-Hang Chen, Yang-Wen Chen, Juinn-Dar Huang","doi":"10.1109/VLSI-DAT.2015.7114494","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114494","url":null,"abstract":"The power dissipation has become a crucial issue for most electronic circuit and system designs nowadays when fabrication processes exploit even deeper submicron technology. In particular, leakage power is becoming a dominant source of power consumption. In recent years, the reconfigurable single-electron transistor (SET) array has been proposed as an emerging circuit design style for continuing Moore's Law due to its ultra-low power consumption. Several automated synthesis techniques for area minimization have been developed for the reconfigurable SET array in the past few years. Nevertheless, most of those existing methods focus on variable and product term reordering during SET mapping. In fact, minimizing the number of product terms can greatly reduce the area as well, which has not been well addressed before. In this paper, we propose a dynamic shifting based variable ordering algorithm that can minimize the number of disjoint sum-of-product terms extracted from the given ROBDD. Experimental results show that the proposed method can achieve an area reduction of up to 49% as compared to current state-of-the-art techniques.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132491891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114525
Abdulkadir Akin, Raffaele Capoccia, Jonathan Narinx, I. Baz, A. Schmid, Y. Leblebici
This paper proposes a hardware-oriented trinocular adaptive window size disparity estimation (T-AWDE) algorithm and the first real-time trinocular disparity estimation (DE) hardware that targets high-resolution images with high-quality disparity results. The proposed trinocular DE hardware is the enhanced version of the recently published binocular AWDE implementation. The T-AWDE hardware generates a very high-quality depth map by merging two depth maps obtained from the center-left and center-right camera pairs. The T-AWDE hardware enhances disparity results by applying a double checking scheme which solves most of the occlusion problems existing in the AWDE implementation while providing correct disparity results even for objects located at left or right edge of the center image. The proposed T-AWDE hardware architecture enables handling 55 frames per second on a Virtex-7 FPGA at a 1024×768 XGA video resolution for a 128 pixels disparity range.
{"title":"Trinocular adaptive window size disparity estimation algorithm and its real-time hardware","authors":"Abdulkadir Akin, Raffaele Capoccia, Jonathan Narinx, I. Baz, A. Schmid, Y. Leblebici","doi":"10.1109/VLSI-DAT.2015.7114525","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114525","url":null,"abstract":"This paper proposes a hardware-oriented trinocular adaptive window size disparity estimation (T-AWDE) algorithm and the first real-time trinocular disparity estimation (DE) hardware that targets high-resolution images with high-quality disparity results. The proposed trinocular DE hardware is the enhanced version of the recently published binocular AWDE implementation. The T-AWDE hardware generates a very high-quality depth map by merging two depth maps obtained from the center-left and center-right camera pairs. The T-AWDE hardware enhances disparity results by applying a double checking scheme which solves most of the occlusion problems existing in the AWDE implementation while providing correct disparity results even for objects located at left or right edge of the center image. The proposed T-AWDE hardware architecture enables handling 55 frames per second on a Virtex-7 FPGA at a 1024×768 XGA video resolution for a 128 pixels disparity range.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121026701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114531
Jai-Ming Lin, Chih-Yao Hu, Kai-Chung Chan
Floorplanning is one of the most important steps in the physical design. Traditional floorplanning focuses on minimizing wirelength and area. As design complexity grows, more and more nets need to be routed in a chip, which makes routing difficulty increase dramatically in modern ICs. Hence, it is necessary to consider net routability during floorplanning. This paper proposes the first work to consider routability and wirelength in floorplanning with fixed-outline constraint by using an analytical based approach. To estimate congestion more accurately, we also propose a new model to measure net usages, and transform the model into differentiable functions such that they can be solved by the optimization approach. The proposed method is efficient and effective, and the experimental results demonstrate the approach can actually reduce overflows without increasing routing wirelength.
{"title":"Routability-driven floorplanning algorithm for mixed-size modules with fixed-outline constraint","authors":"Jai-Ming Lin, Chih-Yao Hu, Kai-Chung Chan","doi":"10.1109/VLSI-DAT.2015.7114531","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114531","url":null,"abstract":"Floorplanning is one of the most important steps in the physical design. Traditional floorplanning focuses on minimizing wirelength and area. As design complexity grows, more and more nets need to be routed in a chip, which makes routing difficulty increase dramatically in modern ICs. Hence, it is necessary to consider net routability during floorplanning. This paper proposes the first work to consider routability and wirelength in floorplanning with fixed-outline constraint by using an analytical based approach. To estimate congestion more accurately, we also propose a new model to measure net usages, and transform the model into differentiable functions such that they can be solved by the optimization approach. The proposed method is efficient and effective, and the experimental results demonstrate the approach can actually reduce overflows without increasing routing wirelength.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130831599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114497
Wei-Xiang Tang, Keng-Yu Lin, Po-Han Haung
This paper reveals an in-house microcontroller, BLAZE, running at 1MHz and 0.4V. In order to deploy BLAZE under strict environments, an on-chip distributed voltage compensator is proposed. With these compensators whose layout size are similar to standard DECAP cell, the voltage stability improves more than 20.3% compared to DECAP cells. To reduce the extra power source and level-shifter a single voltage IO cell is proposed with less than 28% performance degradation. BLAZE is also evaluated for wireless sensing applications, and the results show that BLAZE is more suitable to work under near-threshold regime than race-to-sleep.
{"title":"Design of near-threshold microcontroller for wireless sensing applications","authors":"Wei-Xiang Tang, Keng-Yu Lin, Po-Han Haung","doi":"10.1109/VLSI-DAT.2015.7114497","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114497","url":null,"abstract":"This paper reveals an in-house microcontroller, BLAZE, running at 1MHz and 0.4V. In order to deploy BLAZE under strict environments, an on-chip distributed voltage compensator is proposed. With these compensators whose layout size are similar to standard DECAP cell, the voltage stability improves more than 20.3% compared to DECAP cells. To reduce the extra power source and level-shifter a single voltage IO cell is proposed with less than 28% performance degradation. BLAZE is also evaluated for wireless sensing applications, and the results show that BLAZE is more suitable to work under near-threshold regime than race-to-sleep.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130998167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114534
S. Nishizawa, T. Ishihara, H. Onodera
Dynamic Voltage and Frequency Scaling (DVFS) technique requires accurate observation of critical path delay for robust operation under aggressive supply voltage scaling. Logic paths contain several types of logic gates and path delay have voltage dependences because different logic gates have different voltage dependences. However, it is not well investigated that how the voltage dependence of the path delay changes induced by process variation. This paper describes the effect of the process variation on the voltage dependence of path delay. Ring Oscillator circuits fabricated in 65-nm CMOS process are used for the evaluation and analysis of the process variation dependence of the voltage delay curves.
{"title":"An impact of process variation on supply voltage dependence of logic path delay variation","authors":"S. Nishizawa, T. Ishihara, H. Onodera","doi":"10.1109/VLSI-DAT.2015.7114534","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114534","url":null,"abstract":"Dynamic Voltage and Frequency Scaling (DVFS) technique requires accurate observation of critical path delay for robust operation under aggressive supply voltage scaling. Logic paths contain several types of logic gates and path delay have voltage dependences because different logic gates have different voltage dependences. However, it is not well investigated that how the voltage dependence of the path delay changes induced by process variation. This paper describes the effect of the process variation on the voltage dependence of path delay. Ring Oscillator circuits fabricated in 65-nm CMOS process are used for the evaluation and analysis of the process variation dependence of the voltage delay curves.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123060894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a comparator-based OTA first-order discrete-time low-distortion sigma-delta modulator. A split data weighted averaging (DWA) algorithm logic is proposed to release the heavy burden of digital circuit while a 6 bit DAC is implemented in this work. In addition, a comparator-based OTA is used to reduce the power consumption. On the top of that, to achieve lower power consumption, a power efficient SAR quantizer with embedded analog passive adder is proposed to eliminate additional operational amplifier for summation. The modulator core occupies an active area of 0.0275 mm2 in TSMC 90-nm 1P9M CMOS process. Experimental results show that the proposed modulator achieves 59.90 dB SNDR with 0.58 mW power consumption under 1.0 V supply voltage, an OSR of 16 at 65 MHz sampling frequency and 500kHz input frequency.
{"title":"A first-order low distortion sigma-delta modulator using split DWA technique and SAR quantizer","authors":"Tien-Feng Hsu, Chun-Po Huang, I-Jen Chao, Soon-Jyh Chang","doi":"10.1109/VLSI-DAT.2015.7114518","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114518","url":null,"abstract":"This paper presents a comparator-based OTA first-order discrete-time low-distortion sigma-delta modulator. A split data weighted averaging (DWA) algorithm logic is proposed to release the heavy burden of digital circuit while a 6 bit DAC is implemented in this work. In addition, a comparator-based OTA is used to reduce the power consumption. On the top of that, to achieve lower power consumption, a power efficient SAR quantizer with embedded analog passive adder is proposed to eliminate additional operational amplifier for summation. The modulator core occupies an active area of 0.0275 mm2 in TSMC 90-nm 1P9M CMOS process. Experimental results show that the proposed modulator achieves 59.90 dB SNDR with 0.58 mW power consumption under 1.0 V supply voltage, an OSR of 16 at 65 MHz sampling frequency and 500kHz input frequency.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128950483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a phase noise cancellation (PNC) architecture is presented for 60 GHz communication systems. The BER performance is severely degraded by the non-ideal carrier frequency in 60 GHz bandwidth, which causes both common phase error (CPE) and residual carrier frequency offset (RCFO). The proposed simplified two-stage CPE algorithm solves the RCFO and common phase nose in the frequency domain and eliminates the constellation rotation on each sub-channel. Two-stage architecture together with deep pipelining technique achieves a high throughput rate. This PNC architecture has been implemented in a SC/OFDM Dual-Mode baseband receiver satisfying the requirements of the 802.15.3c/802.11ad standard with a 40 nm process. The proposed PNC is able to support 64QAM/16QAM for OFDM/SC mode, and can achieve up to 19.2 Giga-bit per second (Gbps) throughput rate at 400 MHz operating frequency with power consumption of 33 mW and area of 0.142 mm2.
{"title":"A 802.15.3c/802.11ad dual mode phase noise cancellation for 60 GHz communication systems","authors":"Liang-Yu Huang, Chia-Yi Wu, Chun-Yi Liu, Wei-Chang Liu, Chih-Feng Wu, S. Jou","doi":"10.1109/VLSI-DAT.2015.7114575","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114575","url":null,"abstract":"In this paper, a phase noise cancellation (PNC) architecture is presented for 60 GHz communication systems. The BER performance is severely degraded by the non-ideal carrier frequency in 60 GHz bandwidth, which causes both common phase error (CPE) and residual carrier frequency offset (RCFO). The proposed simplified two-stage CPE algorithm solves the RCFO and common phase nose in the frequency domain and eliminates the constellation rotation on each sub-channel. Two-stage architecture together with deep pipelining technique achieves a high throughput rate. This PNC architecture has been implemented in a SC/OFDM Dual-Mode baseband receiver satisfying the requirements of the 802.15.3c/802.11ad standard with a 40 nm process. The proposed PNC is able to support 64QAM/16QAM for OFDM/SC mode, and can achieve up to 19.2 Giga-bit per second (Gbps) throughput rate at 400 MHz operating frequency with power consumption of 33 mW and area of 0.142 mm2.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130319619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114578
Chia-Jung Chang, Yin-Chi Peng, Chien-Chih Chen, Tien-Fu Chen, P. Yew
For the last decade, there have been varying techniques for hardware prefetching to improve the system performance. However, untimely prefetching may pollution caches and resulting into significant performance degradation. In this work, we introduce an Adaptive Granularity and coordinated Prefetching (AGP) that consists of a coarse-grained and fine-grained prefetched mechanism to provide a better caching environment for parallel applications. AGP targets on the degree-adjusting and location-choosing and tries to minimize the influence caused by prefetcher for each core. AGP could produce more timely prefetched requests reducing the cache pollutions and contentions. Across a variety of PARSEC benchmarks, AGP can contribute 6.5% (up to 36%) of performance improvement on a 4-core multicore system compared to the non-prefetching.
{"title":"Adaptive granularity and coordinated management for timely prefetching in multi-core systems","authors":"Chia-Jung Chang, Yin-Chi Peng, Chien-Chih Chen, Tien-Fu Chen, P. Yew","doi":"10.1109/VLSI-DAT.2015.7114578","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114578","url":null,"abstract":"For the last decade, there have been varying techniques for hardware prefetching to improve the system performance. However, untimely prefetching may pollution caches and resulting into significant performance degradation. In this work, we introduce an Adaptive Granularity and coordinated Prefetching (AGP) that consists of a coarse-grained and fine-grained prefetched mechanism to provide a better caching environment for parallel applications. AGP targets on the degree-adjusting and location-choosing and tries to minimize the influence caused by prefetcher for each core. AGP could produce more timely prefetched requests reducing the cache pollutions and contentions. Across a variety of PARSEC benchmarks, AGP can contribute 6.5% (up to 36%) of performance improvement on a 4-core multicore system compared to the non-prefetching.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130564872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-TSA.2015.7117543
H. Tuan
Summary form only given. Internet of Things (IOT) has caught a lot of attention recently due to tremendous business opportunities. In this talk, the speaker intends to give the historical figures in PC/ NB and smartphones at first, and then bring in the overall view of IOT. And then it will deploy to various semiconductor technology challenges and opportunities for IOT applications, including micro-controllers, micro-processors, wireless technologies, sensors, power managements, etc. The audience should expect to get clearer pictures of devices in IOT from this talk.
{"title":"Semiconductor specialty technologies in IOT era","authors":"H. Tuan","doi":"10.1109/VLSI-TSA.2015.7117543","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2015.7117543","url":null,"abstract":"Summary form only given. Internet of Things (IOT) has caught a lot of attention recently due to tremendous business opportunities. In this talk, the speaker intends to give the historical figures in PC/ NB and smartphones at first, and then bring in the overall view of IOT. And then it will deploy to various semiconductor technology challenges and opportunities for IOT applications, including micro-controllers, micro-processors, wireless technologies, sensors, power managements, etc. The audience should expect to get clearer pictures of devices in IOT from this talk.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132042608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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