Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268529
N. Di Trani, A. Grattoni, M. Ferrari
Management of chronic pathologies requires the development of novel strategies for the delivery of drugs and cell therapies, ad hoc. We have developed implantable micronanofluidic-based platforms that leverage molecular nanoconfinement for the controlled administration of drugs and transplantation of cells. These rely on silicon nanofabricated membranes and 3D-printed polymeric architectures that afford long term function in vivo without complex pumping mechanisms or actuation. In this work, we present our recent advances in zero-order drug delivery implants, remotely tunable delivery devices, and subcutaneous encapsulations for endocrine cells transplantation.
{"title":"Nanofluidics for cell and drug delivery","authors":"N. Di Trani, A. Grattoni, M. Ferrari","doi":"10.1109/IEDM.2017.8268529","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268529","url":null,"abstract":"Management of chronic pathologies requires the development of novel strategies for the delivery of drugs and cell therapies, ad hoc. We have developed implantable micronanofluidic-based platforms that leverage molecular nanoconfinement for the controlled administration of drugs and transplantation of cells. These rely on silicon nanofabricated membranes and 3D-printed polymeric architectures that afford long term function in vivo without complex pumping mechanisms or actuation. In this work, we present our recent advances in zero-order drug delivery implants, remotely tunable delivery devices, and subcutaneous encapsulations for endocrine cells transplantation.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133328320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268360
T. Kimoto, H. Niwa, N. Kaji, T. Kobayashi, Y. Zhao, S. Mori, M. Aketa
Recent progress in SiC device physics and development of power devices in the authors' group is reviewed. The impact ionization coefficients in the wide temperature range were determined, which enables accurate device simulation. 13 kV SiC pin diodes with a very low differential on-resistance of 1.4 mΩ.cm2 and 11 kV SiC epitaxial MPS diodes are presented. A mobility-limiting factor in SiC MOSFETs is discussed, and 3 kV reverse-blocking MOSFETs are demonstrated.
{"title":"Progress and future challenges of SiC power devices and process technology","authors":"T. Kimoto, H. Niwa, N. Kaji, T. Kobayashi, Y. Zhao, S. Mori, M. Aketa","doi":"10.1109/IEDM.2017.8268360","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268360","url":null,"abstract":"Recent progress in SiC device physics and development of power devices in the authors' group is reviewed. The impact ionization coefficients in the wide temperature range were determined, which enables accurate device simulation. 13 kV SiC pin diodes with a very low differential on-resistance of 1.4 mΩ.cm2 and 11 kV SiC epitaxial MPS diodes are presented. A mobility-limiting factor in SiC MOSFETs is discussed, and 3 kV reverse-blocking MOSFETs are demonstrated.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133452618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268394
H. Ota, K. Fukuda, T. Ikegami, J. Hattori, H. Asai, S. Migita, A. Toriumi
Stability and instability of the negative capacitance (NC) states in metal (M) / ferroelectric (F) /M /insulator (I) /semiconductor (S) structures are rigorously studied using a newly developed transient TCAD simulation, in which time-dependent Landau-Khalatnikov (LK) equation can be considered. Our transient analysis reveals that NC becomes unstable due to formation of the inversion layer and gives rise to hysteresis in the NC-state, which cannot be simulated by the steady simulation. We propose a novel FinFET, in which the F-layer is located at the gate contact holes and exhibit a design guideline to avoid the instability of the NC-state using experimentally obtained ferroelectric parameters for (Hf, Zr)O2.
{"title":"Perspective of negative capacitance FinFETs investigated by transient TCAD simulation","authors":"H. Ota, K. Fukuda, T. Ikegami, J. Hattori, H. Asai, S. Migita, A. Toriumi","doi":"10.1109/IEDM.2017.8268394","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268394","url":null,"abstract":"Stability and instability of the negative capacitance (NC) states in metal (M) / ferroelectric (F) /M /insulator (I) /semiconductor (S) structures are rigorously studied using a newly developed transient TCAD simulation, in which time-dependent Landau-Khalatnikov (LK) equation can be considered. Our transient analysis reveals that NC becomes unstable due to formation of the inversion layer and gives rise to hysteresis in the NC-state, which cannot be simulated by the steady simulation. We propose a novel FinFET, in which the F-layer is located at the gate contact holes and exhibit a design guideline to avoid the instability of the NC-state using experimentally obtained ferroelectric parameters for (Hf, Zr)O2.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131944568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268336
T. Agarwal, Á. Szabó, M. Bardon, B. Sorée, I. Radu, P. Raghavan, M. Luisier, W. Dehaene, M. Heyns
In this paper, monolayer transition metal dichalcogenide (MX2) FETs are benchmarked with Si FinFET using energy-delay as figure-of-merits and a physical compact model. The model is validated with the help of both atomistic simulations and experimental data for different materials, without the use of any fitting parameter. Single-gate (SG) and double-gate (DG) MX2 FETs are compared from ON current, device capacitance and energy-delay perspective. DG MX2 FETs perform 25–30% faster than SG MX2 FETs for the same energy consumption in case of dominating wire load. WS2 DG FET shows both better energy and speed among chosen MX2 materials. However, in comparison to FinFET, WS2 DG FETs are shown to be ∼ 35% slower, but more energy efficient. Therefore, to match FinFET's performance with MX2 FETs, monolithic 3D integrated MX2 SG and DG FETs are explored. It is shown that 3–5 stacked WS2 DG FETs are needed to meet N3 FinFET performance.
{"title":"Benchmarking of monolithic 3D integrated MX2 FETs with Si FinFETs","authors":"T. Agarwal, Á. Szabó, M. Bardon, B. Sorée, I. Radu, P. Raghavan, M. Luisier, W. Dehaene, M. Heyns","doi":"10.1109/IEDM.2017.8268336","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268336","url":null,"abstract":"In this paper, monolayer transition metal dichalcogenide (MX2) FETs are benchmarked with Si FinFET using energy-delay as figure-of-merits and a physical compact model. The model is validated with the help of both atomistic simulations and experimental data for different materials, without the use of any fitting parameter. Single-gate (SG) and double-gate (DG) MX2 FETs are compared from ON current, device capacitance and energy-delay perspective. DG MX2 FETs perform 25–30% faster than SG MX2 FETs for the same energy consumption in case of dominating wire load. WS2 DG FET shows both better energy and speed among chosen MX2 materials. However, in comparison to FinFET, WS2 DG FETs are shown to be ∼ 35% slower, but more energy efficient. Therefore, to match FinFET's performance with MX2 FETs, monolithic 3D integrated MX2 SG and DG FETs are explored. It is shown that 3–5 stacked WS2 DG FETs are needed to meet N3 FinFET performance.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132046978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268364
H. Y. Jeong, E.-G. Kim, S. Han, G. Y. Lee, B. Jin, T. Lim, H. C. Kim, T. S. Kim, D. Y. Kim, S. Kwon
For the prompt prescription of patients suffering from infectious diseases such as tuberculosis or bloodstream infection, a rapid antimicrobial susceptibility test (RAST) is highly necessary. This paper describe rapid antibiotic susceptibility test system composed of biochips and automated expert system, which can determine the antibiotic susceptibility of bacteria and mycobacteria derived from various parts of body. With RAST, antibiotic susceptibility was available in six hours, which was conventionally taking more than two days. Device design consideration, clinical verification, commercialization, and application of RAST system to infectious diseases are reviewed.
{"title":"Rapid antibiotic susceptibility testing system: Life saving bioMEMS devices","authors":"H. Y. Jeong, E.-G. Kim, S. Han, G. Y. Lee, B. Jin, T. Lim, H. C. Kim, T. S. Kim, D. Y. Kim, S. Kwon","doi":"10.1109/IEDM.2017.8268364","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268364","url":null,"abstract":"For the prompt prescription of patients suffering from infectious diseases such as tuberculosis or bloodstream infection, a rapid antimicrobial susceptibility test (RAST) is highly necessary. This paper describe rapid antibiotic susceptibility test system composed of biochips and automated expert system, which can determine the antibiotic susceptibility of bacteria and mycobacteria derived from various parts of body. With RAST, antibiotic susceptibility was available in six hours, which was conventionally taking more than two days. Device design consideration, clinical verification, commercialization, and application of RAST system to infectious diseases are reviewed.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121358239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268317
H. Tsugawa, H. Takahashi, R. Nakamura, T. Umebayashi, T. Ogita, H. Okano, K. Iwase, H. Kawashima, T. Yamasaki, D. Yoneyama, J. Hashizume, T. Nakajima, K. Murata, Y. Kanaishi, K. Ikeda, K. Tatani, T. Nagano, H. Nakayama, T. Haruta, T. Nomoto
We developed a CMOS image sensor (CIS) chip, which is stacked pixel/DRAM/logic. In this CIS chip, three Si substrates are bonded together, and each substrate is electrically connected by two-stacked through-silica vias (TSVs) through the CIS or dynamic random access memory (DRAM). We obtained low resistance, low leakage current, and high reliability characteristics of these TSVs. Connecting metal with TSVs through DRAM can be used as low resistance wiring for a power supply. The Si substrate of the DRAM can be thinned to 3 pm, and its memory retention and operation characteristics are sufficient for specifications after thinning. With this stacked CIS chip, it is possible to achieve less rolling shutter distortion and produce super slow motion video.
{"title":"Pixel/DRAM/logic 3-layer stacked CMOS image sensor technology","authors":"H. Tsugawa, H. Takahashi, R. Nakamura, T. Umebayashi, T. Ogita, H. Okano, K. Iwase, H. Kawashima, T. Yamasaki, D. Yoneyama, J. Hashizume, T. Nakajima, K. Murata, Y. Kanaishi, K. Ikeda, K. Tatani, T. Nagano, H. Nakayama, T. Haruta, T. Nomoto","doi":"10.1109/IEDM.2017.8268317","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268317","url":null,"abstract":"We developed a CMOS image sensor (CIS) chip, which is stacked pixel/DRAM/logic. In this CIS chip, three Si substrates are bonded together, and each substrate is electrically connected by two-stacked through-silica vias (TSVs) through the CIS or dynamic random access memory (DRAM). We obtained low resistance, low leakage current, and high reliability characteristics of these TSVs. Connecting metal with TSVs through DRAM can be used as low resistance wiring for a power supply. The Si substrate of the DRAM can be thinned to 3 pm, and its memory retention and operation characteristics are sufficient for specifications after thinning. With this stacked CIS chip, it is possible to achieve less rolling shutter distortion and produce super slow motion video.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129374762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268504
Yang Lv, Jianping Wang
We propose and experimentally demonstrate stochastic computing (SC) with a single magnetic tunnel junction (MJT), exploiting the physical properties and behaviors of the device. Pulse amplitude, bias field, bias current, and pulse width are used as inputs; the output is the switching probability. A single MJT can implement the operations of addition and multiplication. The scheme benefits from the high energy efficiency of an MTJ operated by spintransfer torque (STT), or other future switching mechanisms. Stochastic operations naturally provide high error tolerance, low complexity and low area cost.
{"title":"A single magnetic-tunnel-junction stochastic computing unit","authors":"Yang Lv, Jianping Wang","doi":"10.1109/IEDM.2017.8268504","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268504","url":null,"abstract":"We propose and experimentally demonstrate stochastic computing (SC) with a single magnetic tunnel junction (MJT), exploiting the physical properties and behaviors of the device. Pulse amplitude, bias field, bias current, and pulse width are used as inputs; the output is the switching probability. A single MJT can implement the operations of addition and multiplication. The scheme benefits from the high energy efficiency of an MTJ operated by spintransfer torque (STT), or other future switching mechanisms. Stochastic operations naturally provide high error tolerance, low complexity and low area cost.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128526918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268405
Myung-Jae Lee, A. Ximenes, Preethi Padmanabhan, Tzu-Jui Wang, Kuo-Chin Huang, Y. Yamashita, D. Yaung, E. Charbon
We report on the world's first back-illuminated 3D-stacked single-photon avalanche diode (SPAD) in 45nm CMOS technology. This SPAD achieves a dark count rate of 55.4cps/μm2, a maximum photon detection probability of 31.8% at 600nm, over 5% in the 420–920nm wavelength range, and timing jitter of 107.7ps at 2.5V excess bias voltage and room temperature. To the best of our knowledge, these are the best results ever reported for any back-illuminated 3D-stacked SPAD technology.
{"title":"A back-illuminated 3D-stacked single-photon avalanche diode in 45nm CMOS technology","authors":"Myung-Jae Lee, A. Ximenes, Preethi Padmanabhan, Tzu-Jui Wang, Kuo-Chin Huang, Y. Yamashita, D. Yaung, E. Charbon","doi":"10.1109/IEDM.2017.8268405","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268405","url":null,"abstract":"We report on the world's first back-illuminated 3D-stacked single-photon avalanche diode (SPAD) in 45nm CMOS technology. This SPAD achieves a dark count rate of 55.4cps/μm2, a maximum photon detection probability of 31.8% at 600nm, over 5% in the 420–920nm wavelength range, and timing jitter of 107.7ps at 2.5V excess bias voltage and room temperature. To the best of our knowledge, these are the best results ever reported for any back-illuminated 3D-stacked SPAD technology.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114854661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268339
Abinash Mohanty, Xiaocong Du, Pai-Yu Chen, Jae-sun Seo, Shimeng Yu, Yu Cao
An array of multi-level resistive memory devices (RRAMs) can speed up the computation of deep learning algorithms. However, when a pre-trained model is programmed to a real RRAM array for inference, its accuracy degrades due to many non-idealities, such as variations, quantization error, and stuck-at faults. A conventional solution involves multiple read-verify-write (R-V-W) for each RRAM cell, costing a long time because of the slow Write speed and cell-by-cell compensation. In this work, we propose a fundamentally new approach to overcome this issue: random sparse adaptation (RSA) after the model is transferred to the RRAM array. By randomly selecting a small portion of model parameters and mapping them to on-chip memory for further training, we demonstrate an efficient and fast method to recover the accuracy: in CNNs for MNIST and CIFAR-10, ∼5% of model parameters is sufficient for RSA even under excessive RRAM variations. As the back-propagation in training is only applied to RSA cells and there is no need of any Write operation on RRAM, the proposed RSA achieves 10–100X acceleration compared to R-V-W. Therefore, this hybrid solution with a large, inaccurate RRAM array and a small, accurate on-chip memory array promises both area efficiency and inference accuracy.
{"title":"Random sparse adaptation for accurate inference with inaccurate multi-level RRAM arrays","authors":"Abinash Mohanty, Xiaocong Du, Pai-Yu Chen, Jae-sun Seo, Shimeng Yu, Yu Cao","doi":"10.1109/IEDM.2017.8268339","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268339","url":null,"abstract":"An array of multi-level resistive memory devices (RRAMs) can speed up the computation of deep learning algorithms. However, when a pre-trained model is programmed to a real RRAM array for inference, its accuracy degrades due to many non-idealities, such as variations, quantization error, and stuck-at faults. A conventional solution involves multiple read-verify-write (R-V-W) for each RRAM cell, costing a long time because of the slow Write speed and cell-by-cell compensation. In this work, we propose a fundamentally new approach to overcome this issue: random sparse adaptation (RSA) after the model is transferred to the RRAM array. By randomly selecting a small portion of model parameters and mapping them to on-chip memory for further training, we demonstrate an efficient and fast method to recover the accuracy: in CNNs for MNIST and CIFAR-10, ∼5% of model parameters is sufficient for RSA even under excessive RRAM variations. As the back-propagation in training is only applied to RSA cells and there is no need of any Write operation on RRAM, the proposed RSA achieves 10–100X acceleration compared to R-V-W. Therefore, this hybrid solution with a large, inaccurate RRAM array and a small, accurate on-chip memory array promises both area efficiency and inference accuracy.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126034625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268472
C. Auth, A. Aliyarukunju, M. Asoro, D. Bergstrom, V. Bhagwat, J. Birdsall, N. Bisnik, M. Buehler, V. Chikarmane, G. Ding, Q. Fu, H. Gomez, W. Han, D. Hanken, M. Haran, M. Hattendorf, R. Heussner, H. Hiramatsu, B. Ho, S. Jaloviar, I. Jin, S. Joshi, S. Kirby, S. Kosaraju, H. Kothari, G. Leatherman, K. Lee, J. Leib, A. Madhavan, K. Marla, H. Meyer, T. Mule, C. Parker, S. Parthasarathy, C. Pelto, L. Pipes, I. Post, M. Prince, A. Rahman, S. Rajamani, A. Saha, J. D. Santos, M. Sharma, V. Sharma, J. Shin, P. Sinha, P. Smith, M. Sprinkle, A. Amour, C. Staus, R. Suri, D. Towner, A. Tripathi, A. Tura, C. Ward, A. Yeoh
A 10nm logic technology using 3rd-generation FinFET transistors with Self-Aligned Quad Patterning (SAQP) for critical patterning layers, and cobalt local interconnects at three local interconnect layers is described. For high density, a novel self-aligned contact over active gate process and elimination of the dummy gate at cell boundaries are introduced. The transistors feature rectangular fins with 7nm fin width and 46nm fin height, 5th generation high-k metal gate, and 7th-generation strained silicon. Four or six workfunction metal stacks are used to enable undoped fins for low Vt, standard Vt and optional high Vt devices. Interconnects feature 12 metal layers with ultra-low-k dielectrics throughout the interconnect stack. The highest drive currents with the highest cell densities are reported for a 10nm technology.
{"title":"A 10nm high performance and low-power CMOS technology featuring 3rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects","authors":"C. Auth, A. Aliyarukunju, M. Asoro, D. Bergstrom, V. Bhagwat, J. Birdsall, N. Bisnik, M. Buehler, V. Chikarmane, G. Ding, Q. Fu, H. Gomez, W. Han, D. Hanken, M. Haran, M. Hattendorf, R. Heussner, H. Hiramatsu, B. Ho, S. Jaloviar, I. Jin, S. Joshi, S. Kirby, S. Kosaraju, H. Kothari, G. Leatherman, K. Lee, J. Leib, A. Madhavan, K. Marla, H. Meyer, T. Mule, C. Parker, S. Parthasarathy, C. Pelto, L. Pipes, I. Post, M. Prince, A. Rahman, S. Rajamani, A. Saha, J. D. Santos, M. Sharma, V. Sharma, J. Shin, P. Sinha, P. Smith, M. Sprinkle, A. Amour, C. Staus, R. Suri, D. Towner, A. Tripathi, A. Tura, C. Ward, A. Yeoh","doi":"10.1109/IEDM.2017.8268472","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268472","url":null,"abstract":"A 10nm logic technology using 3rd-generation FinFET transistors with Self-Aligned Quad Patterning (SAQP) for critical patterning layers, and cobalt local interconnects at three local interconnect layers is described. For high density, a novel self-aligned contact over active gate process and elimination of the dummy gate at cell boundaries are introduced. The transistors feature rectangular fins with 7nm fin width and 46nm fin height, 5th generation high-k metal gate, and 7th-generation strained silicon. Four or six workfunction metal stacks are used to enable undoped fins for low Vt, standard Vt and optional high Vt devices. Interconnects feature 12 metal layers with ultra-low-k dielectrics throughout the interconnect stack. The highest drive currents with the highest cell densities are reported for a 10nm technology.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121679631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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