Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268490
T. Yonehara, Y. Kajiwara, D. Kato, K. Uesugi, T. Shimizu, Y. Nishida, H. Ono, A. Shindome, A. Mukai, A. Yoshioka, M. Kuraguchi
Threshold voltage shift of GaN MOSFET in positive bias temperature instability test was drastically suppressed by reducing certain impurity densities in SiO2 gate dielectric. An analysis to estimate the charge trap level showed electron traps in the gate dielectric caused the threshold voltage shift in GaN MOSFETs. Moreover, impurities, which formed the electron traps in SiO2, were controlled by heat treatment after SiO2 deposition, and the threshold voltage shift characteristic was improved by the reduction of the impurity densities.
{"title":"Improvement of positive bias temperature instability characteristic in GaN MOSFETs by control of impurity density in SiO2 gate dielectric","authors":"T. Yonehara, Y. Kajiwara, D. Kato, K. Uesugi, T. Shimizu, Y. Nishida, H. Ono, A. Shindome, A. Mukai, A. Yoshioka, M. Kuraguchi","doi":"10.1109/IEDM.2017.8268490","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268490","url":null,"abstract":"Threshold voltage shift of GaN MOSFET in positive bias temperature instability test was drastically suppressed by reducing certain impurity densities in SiO2 gate dielectric. An analysis to estimate the charge trap level showed electron traps in the gate dielectric caused the threshold voltage shift in GaN MOSFETs. Moreover, impurities, which formed the electron traps in SiO2, were controlled by heat treatment after SiO2 deposition, and the threshold voltage shift characteristic was improved by the reduction of the impurity densities.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"328 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115874565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268515
Guohan Hu, Matthias Georg Gottwald, Qing He, Joon-Min Park, G. Lauer, Janusz J. Nowak, S. Brown, B. Doris, D. Edelstein, E. Evarts, Pouya Hashemi, B. Khan, Young-Hwan Kim, C. Kothandaraman, P. MarchackNathan, E. O'Sullivan, M. Reuter, R. Robertazzi, Jonathan Z. Sun, T. Suwannasiri, P. Trouilloud, Y. Zhu, D. Worledge
We report the impact of four key parameters on switching efficiency of STT-MRAM devices with perpendicular magnetic anisotropy: device size, device resistance-area product (RA), blanket film Gilbert damping constant (a), and process temperature. Performance degradation observed in 400°C-processed devices was eliminated by optimizing the perpendicular magnetic tunnel junction (p-MTJ) materials. Furthermore, 400°C-compatible double MTJs were developed for the first time and showed 1.5x improvement in switching efficiency compared to single MTJs with identical free layers.
{"title":"Key parameters affecting STT-MRAM switching efficiency and improved device performance of 400°C-compatible p-MTJs","authors":"Guohan Hu, Matthias Georg Gottwald, Qing He, Joon-Min Park, G. Lauer, Janusz J. Nowak, S. Brown, B. Doris, D. Edelstein, E. Evarts, Pouya Hashemi, B. Khan, Young-Hwan Kim, C. Kothandaraman, P. MarchackNathan, E. O'Sullivan, M. Reuter, R. Robertazzi, Jonathan Z. Sun, T. Suwannasiri, P. Trouilloud, Y. Zhu, D. Worledge","doi":"10.1109/IEDM.2017.8268515","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268515","url":null,"abstract":"We report the impact of four key parameters on switching efficiency of STT-MRAM devices with perpendicular magnetic anisotropy: device size, device resistance-area product (RA), blanket film Gilbert damping constant (a), and process temperature. Performance degradation observed in 400°C-processed devices was eliminated by optimizing the perpendicular magnetic tunnel junction (p-MTJ) materials. Furthermore, 400°C-compatible double MTJs were developed for the first time and showed 1.5x improvement in switching efficiency compared to single MTJs with identical free layers.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129559503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268442
N. Okada, N. Uchida, S. Ogawa, K. Endo, T. Kanayama
The insertion of an amorphous WSin (n = 12) film composed of W-atom-encapsulated Sin cage clusters is demonstrated to reduce the SBH to 0.32 eV at W/n-Si and to 0.51 eV at W/Ge/p-Si junctions, while significantly extending the estimated TDDB lifetime to > 10 years at 100 °C under 5 MV/cm stress for Cu MOS capacitors. This film was formed with an excellent contact hole coverage by using WF6 and SiH4 gas sources in a hot-wall thermal reactor. These film properties enable the direct Cu contact at S/D in CMOS.
{"title":"Cluster-preforming-deposited amorphous WSin (n = 12) insertion film of low SBH and high diffusion barrier for direct Cu contact","authors":"N. Okada, N. Uchida, S. Ogawa, K. Endo, T. Kanayama","doi":"10.1109/IEDM.2017.8268442","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268442","url":null,"abstract":"The insertion of an amorphous WSin (n = 12) film composed of W-atom-encapsulated Sin cage clusters is demonstrated to reduce the SBH to 0.32 eV at W/n-Si and to 0.51 eV at W/Ge/p-Si junctions, while significantly extending the estimated TDDB lifetime to > 10 years at 100 °C under 5 MV/cm stress for Cu MOS capacitors. This film was formed with an excellent contact hole coverage by using WF6 and SiH4 gas sources in a hot-wall thermal reactor. These film properties enable the direct Cu contact at S/D in CMOS.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122131480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268495
C. Baudot, M. Douix, S. Guerber, S. Crémer, N. Vulliet, J. Planchot, Romuald Blanc, L. Babaud, C. Alonso‐Ramos, D. Benedikovich, D. Pérez-Galacho, S. Messaoudene, Sébastien Kerdilès, P. Acosta-Alba, C. Euvrard-Colnat, E. Cassan, D. Marris-Morini, L. Vivien, F. Boeuf
Silicon photonics technological platforms are meant to generate derivative products and concurrently to benefit from the main advantages associated with CMOS platforms namely: high yield, system robustness, product reliability and large volume, low cost production. Nevertheless, a simultaneous innovative approach is to analogously take advantage from state-of-the-art fabrication methods and tools available in CMOS to develop new solutions and propose better performing devices to the platform.
{"title":"Developments in 300mm silicon photonics using traditional CMOS fabrication methods and materials","authors":"C. Baudot, M. Douix, S. Guerber, S. Crémer, N. Vulliet, J. Planchot, Romuald Blanc, L. Babaud, C. Alonso‐Ramos, D. Benedikovich, D. Pérez-Galacho, S. Messaoudene, Sébastien Kerdilès, P. Acosta-Alba, C. Euvrard-Colnat, E. Cassan, D. Marris-Morini, L. Vivien, F. Boeuf","doi":"10.1109/IEDM.2017.8268495","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268495","url":null,"abstract":"Silicon photonics technological platforms are meant to generate derivative products and concurrently to benefit from the main advantages associated with CMOS platforms namely: high yield, system robustness, product reliability and large volume, low cost production. Nevertheless, a simultaneous innovative approach is to analogously take advantage from state-of-the-art fabrication methods and tools available in CMOS to develop new solutions and propose better performing devices to the platform.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127600361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268372
Huaqiang Wu, Peng Yao, B. Gao, Wei Wu, Qingtian Zhang, Wenqiang Zhang, Ning Deng, Dong Wu, H. Wong, Shimeng Yu, H. Qian
RRAM is a promising electrical synaptic device for efficient neuromorphic computing. A human face recognition task was demonstrated on a 1k-bit 1T1R array using an online training perceptron network. The RRAM device structure and materials stack were optimized to achieve reliable bidirectional analog switching behavior. A binarized-hidden-layer (BHL) circuit architecture is proposed to minimize the needs of A/D and D/A converters between RRAM crossbars. Several RRAM non-ideal characteristics were carefully evaluated for handwritten digits' recognition task with proposed BHL architecture and modified neural network algorithm.
{"title":"Device and circuit optimization of RRAM for neuromorphic computing","authors":"Huaqiang Wu, Peng Yao, B. Gao, Wei Wu, Qingtian Zhang, Wenqiang Zhang, Ning Deng, Dong Wu, H. Wong, Shimeng Yu, H. Qian","doi":"10.1109/IEDM.2017.8268372","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268372","url":null,"abstract":"RRAM is a promising electrical synaptic device for efficient neuromorphic computing. A human face recognition task was demonstrated on a 1k-bit 1T1R array using an online training perceptron network. The RRAM device structure and materials stack were optimized to achieve reliable bidirectional analog switching behavior. A binarized-hidden-layer (BHL) circuit architecture is proposed to minimize the needs of A/D and D/A converters between RRAM crossbars. Several RRAM non-ideal characteristics were carefully evaluated for handwritten digits' recognition task with proposed BHL architecture and modified neural network algorithm.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126715036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268346
S.-H. Chen, G. Hellings, D. Linten, T. Chiarella, H. Mertens, R. Boschke, J. Mitard, S. Kubicek, R. Ritzenthaler, E. Bury, N. Wang, G. Groeseneken, A. Mocuta, N. Horiguchi
Beyond dimensional scaling, new process options in CMOS roadmap often result in degradation of ESD device performance. Using 3D TCAD and ESD characterization, the impacts of device architecture, middle-of-line contact scheme, and S/D epitaxy process options are explored on ESD diode performance in next generation bulk FF and GAA technologies.
{"title":"Towards optimal ESD diodes in next generation bulk FinFET and GAA NW technology nodes","authors":"S.-H. Chen, G. Hellings, D. Linten, T. Chiarella, H. Mertens, R. Boschke, J. Mitard, S. Kubicek, R. Ritzenthaler, E. Bury, N. Wang, G. Groeseneken, A. Mocuta, N. Horiguchi","doi":"10.1109/IEDM.2017.8268346","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268346","url":null,"abstract":"Beyond dimensional scaling, new process options in CMOS roadmap often result in degradation of ESD device performance. Using 3D TCAD and ESD characterization, the impacts of device architecture, middle-of-line contact scheme, and S/D epitaxy process options are explored on ESD diode performance in next generation bulk FF and GAA technologies.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122268698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268376
Yachuan Pang, Huaqiang Wu, B. Gao, Dong Wu, An Chen, H. Qian
Physical unclonable function (PUF) is an important hardware security primitive. This paper proposes a novel PUF design based on a double-layer RRAM array architecture and digital RRAM programming achieved by splitting resistance distribution after a continuous distribution was formed. The proposed PUF was implemented on a 16 Mb RRAM test chip and its randomness was verified with NIST test suite. The experimental results demonstrate strong reliability and significantly enhanced resistance against machine-learning attack of this novel PUF design.
{"title":"A novel PUF against machine learning attack: Implementation on a 16 Mb RRAM chip","authors":"Yachuan Pang, Huaqiang Wu, B. Gao, Dong Wu, An Chen, H. Qian","doi":"10.1109/IEDM.2017.8268376","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268376","url":null,"abstract":"Physical unclonable function (PUF) is an important hardware security primitive. This paper proposes a novel PUF design based on a double-layer RRAM array architecture and digital RRAM programming achieved by splitting resistance distribution after a continuous distribution was formed. The proposed PUF was implemented on a 16 Mb RRAM test chip and its randomness was verified with NIST test suite. The experimental results demonstrate strong reliability and significantly enhanced resistance against machine-learning attack of this novel PUF design.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122879565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268447
M. Si, Chunsheng Jiang, C. Su, Y. Tang, Lingming Yang, W. Chung, Muhammad A. Alam, Peide D. Ye
Steep-slope MoS2 NC-FETs with ferroelectric HZO and internal metal gate in the gate dielectric stack are demonstrated. SS less than 50 mV/dec is obtained for both forward and reverse gate voltage sweeps, with minimum SSfor = 37.6 mV/dec and minimum SSRev = 42.2 mV/dec. A second minimum of SSrev as low as 8.3 mV/dec can be measured as the result of dynamic switching at high speed in ferroelectric HZO. The impact of parasitic capacitance on SS and dynamic hysteresis is systematically studied by both experiment and dynamic simulation.
{"title":"Sub-60 mV/dec ferroelectric HZO MoS2 negative capacitance field-effect transistor with internal metal gate: The role of parasitic capacitance","authors":"M. Si, Chunsheng Jiang, C. Su, Y. Tang, Lingming Yang, W. Chung, Muhammad A. Alam, Peide D. Ye","doi":"10.1109/IEDM.2017.8268447","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268447","url":null,"abstract":"Steep-slope MoS2 NC-FETs with ferroelectric HZO and internal metal gate in the gate dielectric stack are demonstrated. SS less than 50 mV/dec is obtained for both forward and reverse gate voltage sweeps, with minimum SSfor = 37.6 mV/dec and minimum SSRev = 42.2 mV/dec. A second minimum of SSrev as low as 8.3 mV/dec can be measured as the result of dynamic switching at high speed in ferroelectric HZO. The impact of parasitic capacitance on SS and dynamic hysteresis is systematically studied by both experiment and dynamic simulation.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126757806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268352
W. Tan, Li Huang, Rui Jie Ng, Lin Wang, K. Ang
We demonstrate a novel black phosphorus carbide (b-PC) phototransistor with a wide absorption spectrum that spans most molecular fingerprints till 8,000 nm and a tunable responsivity and response time at an excitation wavelength of 2,004 nm. The b-PC phototransistor achieves a high responsivity (R) of 2,163 A/W and a short response time of 5.6 ps, which renders it suitable for high speed and weak signal sensing. Its noise-equivalent-power NEPshot ∼ 1.3 fW/Hz1/2 indicates infrared radiation in the femto-watt range can be detected above the shot noise level of this phototransistor. Under the same excitation power, its responsivity and detectivity performance in ambient and room temperature conditions are currently ahead of all recent top performing photodetectors based on 2D materials, showing promise for future internet-of-things (IoT) applications.
我们展示了一种新型的黑碳化磷(b-PC)光电晶体管，其吸收光谱宽，可跨越大多数分子指纹直至8,000 nm，并且在激发波长为2004 nm时具有可调的响应率和响应时间。b-PC光电晶体管具有2163 a /W的高响应率(R)和5.6 ps的短响应时间，适用于高速和弱信号检测。它的噪声当量功率NEPshot ~ 1.3 fW/Hz1/2表明，在该光电晶体管的散粒噪声水平之上，可以检测到飞瓦范围内的红外辐射。在相同的激励功率下，其在环境和室温条件下的响应性和探测性能目前领先于最近所有基于2D材料的高性能光电探测器，显示出未来物联网(IoT)应用的前景。
{"title":"Black phosphorus carbide infrared phototransistor with wide spectrum sensing for IoT applications","authors":"W. Tan, Li Huang, Rui Jie Ng, Lin Wang, K. Ang","doi":"10.1109/IEDM.2017.8268352","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268352","url":null,"abstract":"We demonstrate a novel black phosphorus carbide (b-PC) phototransistor with a wide absorption spectrum that spans most molecular fingerprints till 8,000 nm and a tunable responsivity and response time at an excitation wavelength of 2,004 nm. The b-PC phototransistor achieves a high responsivity (R) of 2,163 A/W and a short response time of 5.6 ps, which renders it suitable for high speed and weak signal sensing. Its noise-equivalent-power NEPshot ∼ 1.3 fW/Hz1/2 indicates infrared radiation in the femto-watt range can be detected above the shot noise level of this phototransistor. Under the same excitation power, its responsivity and detectivity performance in ambient and room temperature conditions are currently ahead of all recent top performing photodetectors based on 2D materials, showing promise for future internet-of-things (IoT) applications.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126573638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268451
D. Stange, N. von den Driesch, D. Rainko, T. Zabel, B. Marzban, Z. Ikonić, P. Zaumseil, G. Capellini, S. Manti, J. Witzens, H. Sigg, D. Grützmacher, D. Buca
The development of a light source on Si, which can be integrated in photonic circuits together with CMOS electronics, is an outstanding goal in the field of Silicon photonics. This could e.g. help to overcome bandwidth limitations and losses of copper interconnects as the number of high-speed transistors on a chip increases. Here, we discuss direct bandgap group IV materials, GeSn/SiGeSn heterostructures and resulting quantum confinement effects for laser implementation. After material characterization, optical properties, including lasing, are probed via photoluminescence spectrometry. The quantum confinement effect in GeSn wells of different thicknesses is investigated. Theoretical calculations show strong quantum confinement to be undesirable past a certain level, as the very different effective masses of r and L electrons lead to a decrease of the L-to Γ-valley energy difference. A main limiting factor for lasing devices turns out to be the defective region at the interface to the Ge substrate due to the high lattice mismatch to GeSn. The use of buffer technology and subsequent pseudomorphic growth of multi-quantum-wells structures offers confinement of carriers in the active material, far from the misfit dislocations region. Performance is strongly boosted, as a reduction of lasing thresholds from 300 kW/cm2 for bulk devices to below 45 kW/cm2 in multi-quantum-well lasers is observed at low temperatures, with the reduction in threshold far outpacing the reduction in active gain material volume.
{"title":"Quantum confinement effects in GeSn/SiGeSn heterostructure lasers","authors":"D. Stange, N. von den Driesch, D. Rainko, T. Zabel, B. Marzban, Z. Ikonić, P. Zaumseil, G. Capellini, S. Manti, J. Witzens, H. Sigg, D. Grützmacher, D. Buca","doi":"10.1109/IEDM.2017.8268451","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268451","url":null,"abstract":"The development of a light source on Si, which can be integrated in photonic circuits together with CMOS electronics, is an outstanding goal in the field of Silicon photonics. This could e.g. help to overcome bandwidth limitations and losses of copper interconnects as the number of high-speed transistors on a chip increases. Here, we discuss direct bandgap group IV materials, GeSn/SiGeSn heterostructures and resulting quantum confinement effects for laser implementation. After material characterization, optical properties, including lasing, are probed via photoluminescence spectrometry. The quantum confinement effect in GeSn wells of different thicknesses is investigated. Theoretical calculations show strong quantum confinement to be undesirable past a certain level, as the very different effective masses of r and L electrons lead to a decrease of the L-to Γ-valley energy difference. A main limiting factor for lasing devices turns out to be the defective region at the interface to the Ge substrate due to the high lattice mismatch to GeSn. The use of buffer technology and subsequent pseudomorphic growth of multi-quantum-wells structures offers confinement of carriers in the active material, far from the misfit dislocations region. Performance is strongly boosted, as a reduction of lasing thresholds from 300 kW/cm2 for bulk devices to below 45 kW/cm2 in multi-quantum-well lasers is observed at low temperatures, with the reduction in threshold far outpacing the reduction in active gain material volume.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127038221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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