Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268346
S.-H. Chen, G. Hellings, D. Linten, T. Chiarella, H. Mertens, R. Boschke, J. Mitard, S. Kubicek, R. Ritzenthaler, E. Bury, N. Wang, G. Groeseneken, A. Mocuta, N. Horiguchi
Beyond dimensional scaling, new process options in CMOS roadmap often result in degradation of ESD device performance. Using 3D TCAD and ESD characterization, the impacts of device architecture, middle-of-line contact scheme, and S/D epitaxy process options are explored on ESD diode performance in next generation bulk FF and GAA technologies.
{"title":"Towards optimal ESD diodes in next generation bulk FinFET and GAA NW technology nodes","authors":"S.-H. Chen, G. Hellings, D. Linten, T. Chiarella, H. Mertens, R. Boschke, J. Mitard, S. Kubicek, R. Ritzenthaler, E. Bury, N. Wang, G. Groeseneken, A. Mocuta, N. Horiguchi","doi":"10.1109/IEDM.2017.8268346","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268346","url":null,"abstract":"Beyond dimensional scaling, new process options in CMOS roadmap often result in degradation of ESD device performance. Using 3D TCAD and ESD characterization, the impacts of device architecture, middle-of-line contact scheme, and S/D epitaxy process options are explored on ESD diode performance in next generation bulk FF and GAA technologies.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122268698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268447
M. Si, Chunsheng Jiang, C. Su, Y. Tang, Lingming Yang, W. Chung, Muhammad A. Alam, Peide D. Ye
Steep-slope MoS2 NC-FETs with ferroelectric HZO and internal metal gate in the gate dielectric stack are demonstrated. SS less than 50 mV/dec is obtained for both forward and reverse gate voltage sweeps, with minimum SSfor = 37.6 mV/dec and minimum SSRev = 42.2 mV/dec. A second minimum of SSrev as low as 8.3 mV/dec can be measured as the result of dynamic switching at high speed in ferroelectric HZO. The impact of parasitic capacitance on SS and dynamic hysteresis is systematically studied by both experiment and dynamic simulation.
{"title":"Sub-60 mV/dec ferroelectric HZO MoS2 negative capacitance field-effect transistor with internal metal gate: The role of parasitic capacitance","authors":"M. Si, Chunsheng Jiang, C. Su, Y. Tang, Lingming Yang, W. Chung, Muhammad A. Alam, Peide D. Ye","doi":"10.1109/IEDM.2017.8268447","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268447","url":null,"abstract":"Steep-slope MoS2 NC-FETs with ferroelectric HZO and internal metal gate in the gate dielectric stack are demonstrated. SS less than 50 mV/dec is obtained for both forward and reverse gate voltage sweeps, with minimum SSfor = 37.6 mV/dec and minimum SSRev = 42.2 mV/dec. A second minimum of SSrev as low as 8.3 mV/dec can be measured as the result of dynamic switching at high speed in ferroelectric HZO. The impact of parasitic capacitance on SS and dynamic hysteresis is systematically studied by both experiment and dynamic simulation.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126757806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268451
D. Stange, N. von den Driesch, D. Rainko, T. Zabel, B. Marzban, Z. Ikonić, P. Zaumseil, G. Capellini, S. Manti, J. Witzens, H. Sigg, D. Grützmacher, D. Buca
The development of a light source on Si, which can be integrated in photonic circuits together with CMOS electronics, is an outstanding goal in the field of Silicon photonics. This could e.g. help to overcome bandwidth limitations and losses of copper interconnects as the number of high-speed transistors on a chip increases. Here, we discuss direct bandgap group IV materials, GeSn/SiGeSn heterostructures and resulting quantum confinement effects for laser implementation. After material characterization, optical properties, including lasing, are probed via photoluminescence spectrometry. The quantum confinement effect in GeSn wells of different thicknesses is investigated. Theoretical calculations show strong quantum confinement to be undesirable past a certain level, as the very different effective masses of r and L electrons lead to a decrease of the L-to Γ-valley energy difference. A main limiting factor for lasing devices turns out to be the defective region at the interface to the Ge substrate due to the high lattice mismatch to GeSn. The use of buffer technology and subsequent pseudomorphic growth of multi-quantum-wells structures offers confinement of carriers in the active material, far from the misfit dislocations region. Performance is strongly boosted, as a reduction of lasing thresholds from 300 kW/cm2 for bulk devices to below 45 kW/cm2 in multi-quantum-well lasers is observed at low temperatures, with the reduction in threshold far outpacing the reduction in active gain material volume.
{"title":"Quantum confinement effects in GeSn/SiGeSn heterostructure lasers","authors":"D. Stange, N. von den Driesch, D. Rainko, T. Zabel, B. Marzban, Z. Ikonić, P. Zaumseil, G. Capellini, S. Manti, J. Witzens, H. Sigg, D. Grützmacher, D. Buca","doi":"10.1109/IEDM.2017.8268451","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268451","url":null,"abstract":"The development of a light source on Si, which can be integrated in photonic circuits together with CMOS electronics, is an outstanding goal in the field of Silicon photonics. This could e.g. help to overcome bandwidth limitations and losses of copper interconnects as the number of high-speed transistors on a chip increases. Here, we discuss direct bandgap group IV materials, GeSn/SiGeSn heterostructures and resulting quantum confinement effects for laser implementation. After material characterization, optical properties, including lasing, are probed via photoluminescence spectrometry. The quantum confinement effect in GeSn wells of different thicknesses is investigated. Theoretical calculations show strong quantum confinement to be undesirable past a certain level, as the very different effective masses of r and L electrons lead to a decrease of the L-to Γ-valley energy difference. A main limiting factor for lasing devices turns out to be the defective region at the interface to the Ge substrate due to the high lattice mismatch to GeSn. The use of buffer technology and subsequent pseudomorphic growth of multi-quantum-wells structures offers confinement of carriers in the active material, far from the misfit dislocations region. Performance is strongly boosted, as a reduction of lasing thresholds from 300 kW/cm2 for bulk devices to below 45 kW/cm2 in multi-quantum-well lasers is observed at low temperatures, with the reduction in threshold far outpacing the reduction in active gain material volume.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127038221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268352
W. Tan, Li Huang, Rui Jie Ng, Lin Wang, K. Ang
We demonstrate a novel black phosphorus carbide (b-PC) phototransistor with a wide absorption spectrum that spans most molecular fingerprints till 8,000 nm and a tunable responsivity and response time at an excitation wavelength of 2,004 nm. The b-PC phototransistor achieves a high responsivity (R) of 2,163 A/W and a short response time of 5.6 ps, which renders it suitable for high speed and weak signal sensing. Its noise-equivalent-power NEPshot ∼ 1.3 fW/Hz1/2 indicates infrared radiation in the femto-watt range can be detected above the shot noise level of this phototransistor. Under the same excitation power, its responsivity and detectivity performance in ambient and room temperature conditions are currently ahead of all recent top performing photodetectors based on 2D materials, showing promise for future internet-of-things (IoT) applications.
我们展示了一种新型的黑碳化磷(b-PC)光电晶体管，其吸收光谱宽，可跨越大多数分子指纹直至8,000 nm，并且在激发波长为2004 nm时具有可调的响应率和响应时间。b-PC光电晶体管具有2163 a /W的高响应率(R)和5.6 ps的短响应时间，适用于高速和弱信号检测。它的噪声当量功率NEPshot ~ 1.3 fW/Hz1/2表明，在该光电晶体管的散粒噪声水平之上，可以检测到飞瓦范围内的红外辐射。在相同的激励功率下，其在环境和室温条件下的响应性和探测性能目前领先于最近所有基于2D材料的高性能光电探测器，显示出未来物联网(IoT)应用的前景。
{"title":"Black phosphorus carbide infrared phototransistor with wide spectrum sensing for IoT applications","authors":"W. Tan, Li Huang, Rui Jie Ng, Lin Wang, K. Ang","doi":"10.1109/IEDM.2017.8268352","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268352","url":null,"abstract":"We demonstrate a novel black phosphorus carbide (b-PC) phototransistor with a wide absorption spectrum that spans most molecular fingerprints till 8,000 nm and a tunable responsivity and response time at an excitation wavelength of 2,004 nm. The b-PC phototransistor achieves a high responsivity (R) of 2,163 A/W and a short response time of 5.6 ps, which renders it suitable for high speed and weak signal sensing. Its noise-equivalent-power NEPshot ∼ 1.3 fW/Hz1/2 indicates infrared radiation in the femto-watt range can be detected above the shot noise level of this phototransistor. Under the same excitation power, its responsivity and detectivity performance in ambient and room temperature conditions are currently ahead of all recent top performing photodetectors based on 2D materials, showing promise for future internet-of-things (IoT) applications.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126573638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268372
Huaqiang Wu, Peng Yao, B. Gao, Wei Wu, Qingtian Zhang, Wenqiang Zhang, Ning Deng, Dong Wu, H. Wong, Shimeng Yu, H. Qian
RRAM is a promising electrical synaptic device for efficient neuromorphic computing. A human face recognition task was demonstrated on a 1k-bit 1T1R array using an online training perceptron network. The RRAM device structure and materials stack were optimized to achieve reliable bidirectional analog switching behavior. A binarized-hidden-layer (BHL) circuit architecture is proposed to minimize the needs of A/D and D/A converters between RRAM crossbars. Several RRAM non-ideal characteristics were carefully evaluated for handwritten digits' recognition task with proposed BHL architecture and modified neural network algorithm.
{"title":"Device and circuit optimization of RRAM for neuromorphic computing","authors":"Huaqiang Wu, Peng Yao, B. Gao, Wei Wu, Qingtian Zhang, Wenqiang Zhang, Ning Deng, Dong Wu, H. Wong, Shimeng Yu, H. Qian","doi":"10.1109/IEDM.2017.8268372","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268372","url":null,"abstract":"RRAM is a promising electrical synaptic device for efficient neuromorphic computing. A human face recognition task was demonstrated on a 1k-bit 1T1R array using an online training perceptron network. The RRAM device structure and materials stack were optimized to achieve reliable bidirectional analog switching behavior. A binarized-hidden-layer (BHL) circuit architecture is proposed to minimize the needs of A/D and D/A converters between RRAM crossbars. Several RRAM non-ideal characteristics were carefully evaluated for handwritten digits' recognition task with proposed BHL architecture and modified neural network algorithm.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126715036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268437
Seong-Wan Ryu, Kyungkyu Min, Jung-Won Shin, Heimi Kwon, Dong-Ho Nam, Tae-Kyung Oh, T. Jang, Min-Soo Yoo, Yong-Taik Kim, Sungjoo Hong
We demonstrated a highly reliable buried-gate saddle-fin cell-transistor (cell-TR) using silicon migration technique of hydrogen (H2) annealing after a dry etch to form the saddle-fin in a fully integrated 2y-nm 4Gb DRAM. It clearly shows a reduction in interface trap density with highly enhanced variable-retention-time (VRT) and Row-Hammering immunity.
{"title":"Overcoming the reliability limitation in the ultimately scaled DRAM using silicon migration technique by hydrogen annealing","authors":"Seong-Wan Ryu, Kyungkyu Min, Jung-Won Shin, Heimi Kwon, Dong-Ho Nam, Tae-Kyung Oh, T. Jang, Min-Soo Yoo, Yong-Taik Kim, Sungjoo Hong","doi":"10.1109/IEDM.2017.8268437","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268437","url":null,"abstract":"We demonstrated a highly reliable buried-gate saddle-fin cell-transistor (cell-TR) using silicon migration technique of hydrogen (H2) annealing after a dry etch to form the saddle-fin in a fully integrated 2y-nm 4Gb DRAM. It clearly shows a reduction in interface trap density with highly enhanced variable-retention-time (VRT) and Row-Hammering immunity.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127539951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268361
Jingshan Wang, Lina Cao, Jinqiao Xie, E. Beam, R. McCarthy, C. Youtsey, P. Fay
High-voltage vertical GaN-on-GaN power diodes with partially compensated ion-implanted edge termination (ET) and sputtered SiNx passivation are reported. The measured devices exhibit a breakdown voltage (Vbr) exceeding 1.2 kV. Optimization of the ion-implantation-based ET has been performed through simulation and experiment, and the impact of SiNx surface passivation on breakdown has also been evaluated. Use of a partially-compensated ET layer, with approximately 40 nm of the p-type anode layer remaining uncompensated by the implant, is optimal for maximizing Vbr. Additionally, sputter-deposited SiNx, rather than the more conventional plasma-enhanced chemical vapor deposition (PECVD)-based SiNx, results in less degradation in the on-state performance while providing the same Vbr. The diodes support current densities of 8 kA/cm2 at a forward voltage 5 V, with differential specific on resistances (Ron) of 0.11 mΩcm2. A Baliga's figure-of merit (BFOM) of 13.5 GW/cm2 is obtained; this is among the highest reported BFOM for GaN homoepitaxial pn diodes.
{"title":"High voltage vertical p-n diodes with ion-implanted edge termination and sputtered SiNx passivation on GaN substrates","authors":"Jingshan Wang, Lina Cao, Jinqiao Xie, E. Beam, R. McCarthy, C. Youtsey, P. Fay","doi":"10.1109/IEDM.2017.8268361","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268361","url":null,"abstract":"High-voltage vertical GaN-on-GaN power diodes with partially compensated ion-implanted edge termination (ET) and sputtered SiNx passivation are reported. The measured devices exhibit a breakdown voltage (Vbr) exceeding 1.2 kV. Optimization of the ion-implantation-based ET has been performed through simulation and experiment, and the impact of SiNx surface passivation on breakdown has also been evaluated. Use of a partially-compensated ET layer, with approximately 40 nm of the p-type anode layer remaining uncompensated by the implant, is optimal for maximizing Vbr. Additionally, sputter-deposited SiNx, rather than the more conventional plasma-enhanced chemical vapor deposition (PECVD)-based SiNx, results in less degradation in the on-state performance while providing the same Vbr. The diodes support current densities of 8 kA/cm2 at a forward voltage 5 V, with differential specific on resistances (Ron) of 0.11 mΩcm2. A Baliga's figure-of merit (BFOM) of 13.5 GW/cm2 is obtained; this is among the highest reported BFOM for GaN homoepitaxial pn diodes.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"468 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127546439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268495
C. Baudot, M. Douix, S. Guerber, S. Crémer, N. Vulliet, J. Planchot, Romuald Blanc, L. Babaud, C. Alonso‐Ramos, D. Benedikovich, D. Pérez-Galacho, S. Messaoudene, Sébastien Kerdilès, P. Acosta-Alba, C. Euvrard-Colnat, E. Cassan, D. Marris-Morini, L. Vivien, F. Boeuf
Silicon photonics technological platforms are meant to generate derivative products and concurrently to benefit from the main advantages associated with CMOS platforms namely: high yield, system robustness, product reliability and large volume, low cost production. Nevertheless, a simultaneous innovative approach is to analogously take advantage from state-of-the-art fabrication methods and tools available in CMOS to develop new solutions and propose better performing devices to the platform.
{"title":"Developments in 300mm silicon photonics using traditional CMOS fabrication methods and materials","authors":"C. Baudot, M. Douix, S. Guerber, S. Crémer, N. Vulliet, J. Planchot, Romuald Blanc, L. Babaud, C. Alonso‐Ramos, D. Benedikovich, D. Pérez-Galacho, S. Messaoudene, Sébastien Kerdilès, P. Acosta-Alba, C. Euvrard-Colnat, E. Cassan, D. Marris-Morini, L. Vivien, F. Boeuf","doi":"10.1109/IEDM.2017.8268495","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268495","url":null,"abstract":"Silicon photonics technological platforms are meant to generate derivative products and concurrently to benefit from the main advantages associated with CMOS platforms namely: high yield, system robustness, product reliability and large volume, low cost production. Nevertheless, a simultaneous innovative approach is to analogously take advantage from state-of-the-art fabrication methods and tools available in CMOS to develop new solutions and propose better performing devices to the platform.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127600361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268351
J. Zhao, Q. Li, Y. Huang, S. Li, W. Tang, S. Peng, S. Chen, W. Liu, X. Guo
A printable device structure design is introduced to fabricate low voltage organic field effect transistor (OFET) of steep subthreshold (80 mV/dec) using thick gate dielectric layers and high throughput printing/coating processes. The device design also bring benefit on excellent bias stress stability. The device is shown to able to be biased in the subthreshold regime with near zero gate voltage for low power and high sensitivity detection of both small H+ concentration (<0.1 pH) and weak fluorescence signal (< 10 μW cm−2) changes.
{"title":"Manufactured-on-demand steep subthreshold organic field effect transistor for low power and high sensitivity ion and fluorescence sensing","authors":"J. Zhao, Q. Li, Y. Huang, S. Li, W. Tang, S. Peng, S. Chen, W. Liu, X. Guo","doi":"10.1109/IEDM.2017.8268351","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268351","url":null,"abstract":"A printable device structure design is introduced to fabricate low voltage organic field effect transistor (OFET) of steep subthreshold (80 mV/dec) using thick gate dielectric layers and high throughput printing/coating processes. The device design also bring benefit on excellent bias stress stability. The device is shown to able to be biased in the subthreshold regime with near zero gate voltage for low power and high sensitivity detection of both small H+ concentration (<0.1 pH) and weak fluorescence signal (< 10 μW cm−2) changes.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116877356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268390
B. Turkot, S. Carson, A. Lio
Extreme Ultra-Violet (EUV) lithography, with its exposure wavelength of 13.5nm, offers a compelling alternative to 193nm-immersion lithography, improving imaging resolution and reducing a key contribution to Edge Placement Error (EPE). Recently, significant progress has been made in the development of EUV exposure tools, with source power meeting the roadmap target for EUV insertion1 as well as demonstrating improvements in system availability and infrastructure such as mask blank defectivity, pellicle membrane manufacturing, and EUV photoresist materials. This paper reviews the current status and challenges of EUV lithography for High Volume Manufacturing (HVM).
{"title":"Continuing Moore's law with EUV lithography","authors":"B. Turkot, S. Carson, A. Lio","doi":"10.1109/IEDM.2017.8268390","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268390","url":null,"abstract":"Extreme Ultra-Violet (EUV) lithography, with its exposure wavelength of 13.5nm, offers a compelling alternative to 193nm-immersion lithography, improving imaging resolution and reducing a key contribution to Edge Placement Error (EPE). Recently, significant progress has been made in the development of EUV exposure tools, with source power meeting the roadmap target for EUV insertion1 as well as demonstrating improvements in system availability and infrastructure such as mask blank defectivity, pellicle membrane manufacturing, and EUV photoresist materials. This paper reviews the current status and challenges of EUV lithography for High Volume Manufacturing (HVM).","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132385657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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