Pub Date : 2015-08-01DOI: 10.1109/RFIT.2015.7377947
Zicheng Liu, Peng Gao, Zhiming Chen
This paper presents a CMOS K-band low noise amplifier (LNA). Pseudo differential structure with on-chip balun has more advantages than single-end in system-on-chip (SOC) and so forth. In this design, two on-chip baluns are inserted in the LNA for single-in and single-out. Some inter-digital capacitors and a transformer are employed for matching to reduce the number of the inductors. The proposed LNA is fabricated in 90 nm CMOS process, achieved a gain of 20dB at 23.5 GHz, a 3-dB bandwidth of 2 GHz (from 22.7 to 24.7 GHz), and a noise figure of 3.6 dB with an input return loss of 17 dB, while consuming 16.5 mW with 1V power supply.
{"title":"A K-band low noise amplifier with on-chip baluns in 90nm CMOS","authors":"Zicheng Liu, Peng Gao, Zhiming Chen","doi":"10.1109/RFIT.2015.7377947","DOIUrl":"https://doi.org/10.1109/RFIT.2015.7377947","url":null,"abstract":"This paper presents a CMOS K-band low noise amplifier (LNA). Pseudo differential structure with on-chip balun has more advantages than single-end in system-on-chip (SOC) and so forth. In this design, two on-chip baluns are inserted in the LNA for single-in and single-out. Some inter-digital capacitors and a transformer are employed for matching to reduce the number of the inductors. The proposed LNA is fabricated in 90 nm CMOS process, achieved a gain of 20dB at 23.5 GHz, a 3-dB bandwidth of 2 GHz (from 22.7 to 24.7 GHz), and a noise figure of 3.6 dB with an input return loss of 17 dB, while consuming 16.5 mW with 1V power supply.","PeriodicalId":422369,"journal":{"name":"2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127875303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/RFIT.2015.7377898
K. Takano, K. Katayama, T. Yoshida, S. Amakawa, M. Fujishima, S. Hara, A. Kasamatsu
In this paper, we propose a calibration method for the parameters of a CMOS process and the structures of transmission lines used in the calibration. The process parameters of each dielectric layer can be determined separately using this method. To verify the proposed method, test structures of four types of transmission lines were fabricated using a 40 nm CMOS process. It was shown that the results of EM simulation using the process parameters calibrated by the proposed method were in good agreement with the measurement results up to 330 GHz.
{"title":"Calibration of process parameters for electromagnetic field analysis of CMOS devices up to 330 GHz","authors":"K. Takano, K. Katayama, T. Yoshida, S. Amakawa, M. Fujishima, S. Hara, A. Kasamatsu","doi":"10.1109/RFIT.2015.7377898","DOIUrl":"https://doi.org/10.1109/RFIT.2015.7377898","url":null,"abstract":"In this paper, we propose a calibration method for the parameters of a CMOS process and the structures of transmission lines used in the calibration. The process parameters of each dielectric layer can be determined separately using this method. To verify the proposed method, test structures of four types of transmission lines were fabricated using a 40 nm CMOS process. It was shown that the results of EM simulation using the process parameters calibrated by the proposed method were in good agreement with the measurement results up to 330 GHz.","PeriodicalId":422369,"journal":{"name":"2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121434089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/RFIT.2015.7377908
Kouhei Nagasawa, Shotaro Fujioka, Kazuhiro Watanabe, Y. Umeda, Y. Kozawa
Power amplifier inserted transversal filter amplifies in high efficiency and can adjust the center frequency and pass bandwidth. In addition, the filter suppresses the quantization noise that remains outside the desired signal band at the output of the filter. The reduction of the quantization noise is due to narrowing the pass bandwidth by increasing the number of paths. However, the circuit scale and the loss in power combining in the filter increase as the number of paths increases. To solve this problem, this paper proposes to use the higher-order passband of the transversal filter to narrowing the filter by increasing the delay difference between adjacent paths of the filter. This realizes passband characteristics almost equivalent to a large number of paths. In addition, this enables to suppress the increase in circuit scale and losses due the power combining. Computer simulation shows that a narrow-band filter can be realized with a small number of paths by using a higher-order passband. It also shows that the degradation in modulation accuracy is small due to the use of higher-order passband.
{"title":"Power-amplifier inserted transversal filter using high-order pass band","authors":"Kouhei Nagasawa, Shotaro Fujioka, Kazuhiro Watanabe, Y. Umeda, Y. Kozawa","doi":"10.1109/RFIT.2015.7377908","DOIUrl":"https://doi.org/10.1109/RFIT.2015.7377908","url":null,"abstract":"Power amplifier inserted transversal filter amplifies in high efficiency and can adjust the center frequency and pass bandwidth. In addition, the filter suppresses the quantization noise that remains outside the desired signal band at the output of the filter. The reduction of the quantization noise is due to narrowing the pass bandwidth by increasing the number of paths. However, the circuit scale and the loss in power combining in the filter increase as the number of paths increases. To solve this problem, this paper proposes to use the higher-order passband of the transversal filter to narrowing the filter by increasing the delay difference between adjacent paths of the filter. This realizes passband characteristics almost equivalent to a large number of paths. In addition, this enables to suppress the increase in circuit scale and losses due the power combining. Computer simulation shows that a narrow-band filter can be realized with a small number of paths by using a higher-order passband. It also shows that the degradation in modulation accuracy is small due to the use of higher-order passband.","PeriodicalId":422369,"journal":{"name":"2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133412819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/RFIT.2015.7377916
N. Suematsu, O. Wada, S. Kameda, T. Takagi, K. Tsubouchi
A 0.8-1.9 GHz direct digital radio frequency (RF) quadrature modulator is designed and fabricated in 90 nm CMOS process. The bit number and the CLK frequency of I/Q digital input signals are designed to satisfy the required EVM, ACPR/NACPR and system bandwidth for 0.9/1.9GHz W-CDMA terminals. The fabricated quadrature modulator performs EVM of less than -22.7dB, ACP/NACP of less than -36.1dBc and spurious free range of 197MHz (wider than the W-CDMA system bandwidth of 60MHz) with 8-bit, 100Msps I/Q digital input signals and the d.c. power consumption of 10mW.
{"title":"A 0.8–1.9GHz-band CMOS direct digital RF quadrature modulator","authors":"N. Suematsu, O. Wada, S. Kameda, T. Takagi, K. Tsubouchi","doi":"10.1109/RFIT.2015.7377916","DOIUrl":"https://doi.org/10.1109/RFIT.2015.7377916","url":null,"abstract":"A 0.8-1.9 GHz direct digital radio frequency (RF) quadrature modulator is designed and fabricated in 90 nm CMOS process. The bit number and the CLK frequency of I/Q digital input signals are designed to satisfy the required EVM, ACPR/NACPR and system bandwidth for 0.9/1.9GHz W-CDMA terminals. The fabricated quadrature modulator performs EVM of less than -22.7dB, ACP/NACP of less than -36.1dBc and spurious free range of 197MHz (wider than the W-CDMA system bandwidth of 60MHz) with 8-bit, 100Msps I/Q digital input signals and the d.c. power consumption of 10mW.","PeriodicalId":422369,"journal":{"name":"2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126496618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/RFIT.2015.7377894
T. Ta, H. Okuni, A. Sai, M. Furuta
To reduce power consumption of the receiver, high-Q matching low noise amplifier (LNA) can be used to reduce the power consumption of the LNA. In this work, we propose a small-size high-accuracy calibration circuit for the high-Q matching LNA. The proposed circuit is constructed by two power detectors and a comparator, which has overall area of 75×35μm2 in a 65 nm CMOS process. By comparing the amplitudes of differential input signals, the optimum setting of the matching circuit is determined. The proposed method can achieve high accuracy matching calibration without the knowledge of the input power. A LNA with proposed calibration circuit is fabricated by 65 nm CMOS process. The evaluation result proves the proposed calibration method effectiveness.
{"title":"A low-power high-Q matching LNA with small-size matching calibration circuit for low power receiver","authors":"T. Ta, H. Okuni, A. Sai, M. Furuta","doi":"10.1109/RFIT.2015.7377894","DOIUrl":"https://doi.org/10.1109/RFIT.2015.7377894","url":null,"abstract":"To reduce power consumption of the receiver, high-Q matching low noise amplifier (LNA) can be used to reduce the power consumption of the LNA. In this work, we propose a small-size high-accuracy calibration circuit for the high-Q matching LNA. The proposed circuit is constructed by two power detectors and a comparator, which has overall area of 75×35μm2 in a 65 nm CMOS process. By comparing the amplitudes of differential input signals, the optimum setting of the matching circuit is determined. The proposed method can achieve high accuracy matching calibration without the knowledge of the input power. A LNA with proposed calibration circuit is fabricated by 65 nm CMOS process. The evaluation result proves the proposed calibration method effectiveness.","PeriodicalId":422369,"journal":{"name":"2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114230664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/RFIT.2015.7377886
Junghwan Yoo, Namhyung Kim, J. Yun, M. Seo, J. Rieh
In this work, a 280-GHz VCO integrated with a frequency divider with a large division ratio is presented. The triple-push Colpitts VCO, fabricated in a 65-nm CMOS technology, showed a tuning range of 279.9-283.0 GHz (3.1 GHz). The divider chain consists of two injection-locked frequency dividers (ILFDs and twelve current-mode logic (CML) dividers With the total division ratio of 16,384, the divider chain successfully divided the fundamental frequency (f0) of the VCO down to near 5.8 MHz. Total DC power consumption of the entire circuit was 131 mW.
{"title":"A CMOS triple-push 280-GHz VCO integrated with 1/16,384 divider chain","authors":"Junghwan Yoo, Namhyung Kim, J. Yun, M. Seo, J. Rieh","doi":"10.1109/RFIT.2015.7377886","DOIUrl":"https://doi.org/10.1109/RFIT.2015.7377886","url":null,"abstract":"In this work, a 280-GHz VCO integrated with a frequency divider with a large division ratio is presented. The triple-push Colpitts VCO, fabricated in a 65-nm CMOS technology, showed a tuning range of 279.9-283.0 GHz (3.1 GHz). The divider chain consists of two injection-locked frequency dividers (ILFDs and twelve current-mode logic (CML) dividers With the total division ratio of 16,384, the divider chain successfully divided the fundamental frequency (f0) of the VCO down to near 5.8 MHz. Total DC power consumption of the entire circuit was 131 mW.","PeriodicalId":422369,"journal":{"name":"2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114668158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/RFIT.2015.7377917
R. Goda, S. Amakawa, K. Katayama, K. Takano, T. Yoshida, M. Fujishima
Wideband decoupling for millimeter-wave circuits can be achieved using a transmission line having an extremely low characteristic impedance. The characteristic impedance of such a line can be estimated at high frequencies by measuring the input impedance of open and shorted stubs. However, since the propagation constant cannot be estimated reliably, a circuit model applicable to low frequencies has not yet been established. In this study, we extract the transmission-line parameters at low frequencies and build a circuit model using the RLGC parameters. This model is verified by comparing the results obtained from a circuit simulation and measurement data up to 40 GHz.
{"title":"Modeling of wideband decoupling power line for millimeter-wave CMOS circuits","authors":"R. Goda, S. Amakawa, K. Katayama, K. Takano, T. Yoshida, M. Fujishima","doi":"10.1109/RFIT.2015.7377917","DOIUrl":"https://doi.org/10.1109/RFIT.2015.7377917","url":null,"abstract":"Wideband decoupling for millimeter-wave circuits can be achieved using a transmission line having an extremely low characteristic impedance. The characteristic impedance of such a line can be estimated at high frequencies by measuring the input impedance of open and shorted stubs. However, since the propagation constant cannot be estimated reliably, a circuit model applicable to low frequencies has not yet been established. In this study, we extract the transmission-line parameters at low frequencies and build a circuit model using the RLGC parameters. This model is verified by comparing the results obtained from a circuit simulation and measurement data up to 40 GHz.","PeriodicalId":422369,"journal":{"name":"2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117123913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/RFIT.2015.7377879
T. Kaho, Y. Yamaguchi, T. Nakagawa, Shinpei Oshima
This paper describes the design and measurement of a quad-band low noise receiver front-end module. It consists of a quintplexer and receiver front-end ICs. The quintplexer is consisted of a low loss triplexer fabricated using low temperature co-fired ceramic (LTCC) technology, a commercial duplexer, and a commercial band-pass filter. The receiver front-end ICs were fabricated using 0.25 μm SiGe BiCMOS process technology and consists of wideband variable gain low noise amplifiers, step attenuators, and down-conversion mixers. The module can concurrently receive quad-band signals in frequencies at 300 MHz, 900 MHz, 2.4GHz, and 5 GHz. The quad-band module is 5 × 5 cm in size. The measured noise figures were under 4.9 dB and the conversion gain were above 24 dB at the frequencies of 300 MHz, 900 MHz, and 2.4 GHz. At the 5GHz frequency, the measured noise figures was under 6.2 dB, and conversion gain was above 16 dB.
{"title":"Quad-band receiver front-end module using SiGe BiCMOS MMICs and LTCC triplexer","authors":"T. Kaho, Y. Yamaguchi, T. Nakagawa, Shinpei Oshima","doi":"10.1109/RFIT.2015.7377879","DOIUrl":"https://doi.org/10.1109/RFIT.2015.7377879","url":null,"abstract":"This paper describes the design and measurement of a quad-band low noise receiver front-end module. It consists of a quintplexer and receiver front-end ICs. The quintplexer is consisted of a low loss triplexer fabricated using low temperature co-fired ceramic (LTCC) technology, a commercial duplexer, and a commercial band-pass filter. The receiver front-end ICs were fabricated using 0.25 μm SiGe BiCMOS process technology and consists of wideband variable gain low noise amplifiers, step attenuators, and down-conversion mixers. The module can concurrently receive quad-band signals in frequencies at 300 MHz, 900 MHz, 2.4GHz, and 5 GHz. The quad-band module is 5 × 5 cm in size. The measured noise figures were under 4.9 dB and the conversion gain were above 24 dB at the frequencies of 300 MHz, 900 MHz, and 2.4 GHz. At the 5GHz frequency, the measured noise figures was under 6.2 dB, and conversion gain was above 16 dB.","PeriodicalId":422369,"journal":{"name":"2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"188 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121239917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/RFIT.2015.7377876
H. Mizutani, E. Taniguchi, M. Tsuru, R. Inagaki, S. Kameda, N. Suematsu, T. Takagi, K. Tsubouchi
This paper presents an optimum interstage matching inductor of a cascode amplifier by formulation, for the first time. The formulation clarifies capacitances of FETs which degrade a gain of the cascode amplifier. The inductive matched cascode LNA fabricated by 90nm CMOS performs 25.6 dB gain with NF of 6 dB and output P1dB of -2.3 dBm at 60GHz while consuming 26.9 mW.
{"title":"An optimum inductive matched cascode LNA in 60GHz-band","authors":"H. Mizutani, E. Taniguchi, M. Tsuru, R. Inagaki, S. Kameda, N. Suematsu, T. Takagi, K. Tsubouchi","doi":"10.1109/RFIT.2015.7377876","DOIUrl":"https://doi.org/10.1109/RFIT.2015.7377876","url":null,"abstract":"This paper presents an optimum interstage matching inductor of a cascode amplifier by formulation, for the first time. The formulation clarifies capacitances of FETs which degrade a gain of the cascode amplifier. The inductive matched cascode LNA fabricated by 90nm CMOS performs 25.6 dB gain with NF of 6 dB and output P1dB of -2.3 dBm at 60GHz while consuming 26.9 mW.","PeriodicalId":422369,"journal":{"name":"2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122700687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a highly linear wideband down-conversion mixer using multiple gated transistor technique (MGTR) is presented. The mixer is designed and fabricated in 0.18-μm 1P6M RF CMOS process. To achieve high IIP3 performance, the MGTR technique is implemented both in the transconductance stage and the output buffer. An achievement of 0.6~7.2 dBm IIP3 operating in the frequency band from 0.045 to 2.5 GHz is attained without significant degradation of gain and noise performance. The post simulation result has indicated a conversion gain of 5.8~8.6dB, a low noise figure of 7.4~9.1dB. The preliminary measured result shows good IF matching (S parameter at the output buffer) of -25.6~-9.1dB. The whole mixer has a compact die area of 0.093 mm2 and a current consumption of 9.1mA under 1.8-V supply voltage.
{"title":"Wideband CMOS mixer using differential circuit transconductance linearization technique","authors":"Lan-qi Liu, Ke-feng Zhang, Zhi-xiong Ren, X. Zou, Zhaojing Lu, Dongsheng Liu","doi":"10.1109/RFIT.2015.7377907","DOIUrl":"https://doi.org/10.1109/RFIT.2015.7377907","url":null,"abstract":"In this paper, a highly linear wideband down-conversion mixer using multiple gated transistor technique (MGTR) is presented. The mixer is designed and fabricated in 0.18-μm 1P6M RF CMOS process. To achieve high IIP3 performance, the MGTR technique is implemented both in the transconductance stage and the output buffer. An achievement of 0.6~7.2 dBm IIP3 operating in the frequency band from 0.045 to 2.5 GHz is attained without significant degradation of gain and noise performance. The post simulation result has indicated a conversion gain of 5.8~8.6dB, a low noise figure of 7.4~9.1dB. The preliminary measured result shows good IF matching (S parameter at the output buffer) of -25.6~-9.1dB. The whole mixer has a compact die area of 0.093 mm2 and a current consumption of 9.1mA under 1.8-V supply voltage.","PeriodicalId":422369,"journal":{"name":"2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124766410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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