Pub Date : 2008-12-09DOI: 10.1109/SMICND.2008.4703357
G. De Pasquale, A. Somà
This work is focused on the design approach to MEMS devices for the energy scavenge; two conversion strategies from vibrations to voltage are considered: electrostatic capacitive and piezoelectric. Main analytical relations for capacitive structures are derived and used for a quantitative estimation of the power scavenged with respect to the operation frequency and to eventual applications.
{"title":"Investigations on energy scavenging methods using MEMS devices","authors":"G. De Pasquale, A. Somà","doi":"10.1109/SMICND.2008.4703357","DOIUrl":"https://doi.org/10.1109/SMICND.2008.4703357","url":null,"abstract":"This work is focused on the design approach to MEMS devices for the energy scavenge; two conversion strategies from vibrations to voltage are considered: electrostatic capacitive and piezoelectric. Main analytical relations for capacitive structures are derived and used for a quantitative estimation of the power scavenged with respect to the operation frequency and to eventual applications.","PeriodicalId":6406,"journal":{"name":"2008 IEEE International Conference on Semiconductor Electronics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81722341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-09DOI: 10.1109/SMICND.2008.4703445
Radu-Sebastian Marinescu, C. Burileanu
The idea of the paper was to develop application for the digital signal controller dsPIC33F. The output waveforms are generated with the DSC, using a DAC, all in a direct-digital synthesis (DDS) system, offering till now sine and square waveform from. The systems is also a good demonstrator for the DDS technique, implemented in a new architectural mode.
{"title":"Function generator by direct-digital frequency synthesis","authors":"Radu-Sebastian Marinescu, C. Burileanu","doi":"10.1109/SMICND.2008.4703445","DOIUrl":"https://doi.org/10.1109/SMICND.2008.4703445","url":null,"abstract":"The idea of the paper was to develop application for the digital signal controller dsPIC33F. The output waveforms are generated with the DSC, using a DAC, all in a direct-digital synthesis (DDS) system, offering till now sine and square waveform from. The systems is also a good demonstrator for the DDS technique, implemented in a new architectural mode.","PeriodicalId":6406,"journal":{"name":"2008 IEEE International Conference on Semiconductor Electronics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79053879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-09DOI: 10.1109/SMICND.2008.4703425
Hadi Hosseinzadegan, H. Aghababa, Mahmoud Zangeneh, A. Afzali-Kusha, B. Forouzandeh
We report deriving a compact model for CNTFETs, using modified current- voltage relations, commonly used in modeling of CNTFETs. A carbon nanotube with 1.7 nm diameter and 5 nm length has been simulated with a layer of ZrO2 as oxide layer. The thickness of the oxide layer has been considered to be 2 nm. Density of states as a function of Fermi level is considered quadratic for both subthreshold and saturation regime. In this paper, the CNTFET drain current and energy level is derived analytically. Finally, the variation of CNTFET drain current versus gate-source and drain-source voltages will be presented though simulation.
{"title":"A compact current-voltage model for carbon nanotube field effect transistors","authors":"Hadi Hosseinzadegan, H. Aghababa, Mahmoud Zangeneh, A. Afzali-Kusha, B. Forouzandeh","doi":"10.1109/SMICND.2008.4703425","DOIUrl":"https://doi.org/10.1109/SMICND.2008.4703425","url":null,"abstract":"We report deriving a compact model for CNTFETs, using modified current- voltage relations, commonly used in modeling of CNTFETs. A carbon nanotube with 1.7 nm diameter and 5 nm length has been simulated with a layer of ZrO2 as oxide layer. The thickness of the oxide layer has been considered to be 2 nm. Density of states as a function of Fermi level is considered quadratic for both subthreshold and saturation regime. In this paper, the CNTFET drain current and energy level is derived analytically. Finally, the variation of CNTFET drain current versus gate-source and drain-source voltages will be presented though simulation.","PeriodicalId":6406,"journal":{"name":"2008 IEEE International Conference on Semiconductor Electronics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87778854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-09DOI: 10.1109/SMICND.2008.4703422
N. Constantin, S. Sorohan, M. Găvan, V. Anghel, V. Raeţchi
In the paper are presented the results obtained by numerical simulations on composite plates, with arrays of transducers able to create guided waves by appropriate management of the signal delay and topology of the transducers. Appropriate generation of the Lamb waves, using an adequately shaped burst signal and frequencies corresponding to quasi non-dispersive modes, proved to be able to detect barely visible defects in composites. The avoidance of reflected signals offered conditions to have an easier analysis task in evaluating the transmitted and reflected waves produced by a guided wave which was scanning the plate or pipe type structure.
{"title":"Effect of frequency and phase setting in obtaining scanning guided waves in composite plates","authors":"N. Constantin, S. Sorohan, M. Găvan, V. Anghel, V. Raeţchi","doi":"10.1109/SMICND.2008.4703422","DOIUrl":"https://doi.org/10.1109/SMICND.2008.4703422","url":null,"abstract":"In the paper are presented the results obtained by numerical simulations on composite plates, with arrays of transducers able to create guided waves by appropriate management of the signal delay and topology of the transducers. Appropriate generation of the Lamb waves, using an adequately shaped burst signal and frequencies corresponding to quasi non-dispersive modes, proved to be able to detect barely visible defects in composites. The avoidance of reflected signals offered conditions to have an easier analysis task in evaluating the transmitted and reflected waves produced by a guided wave which was scanning the plate or pipe type structure.","PeriodicalId":6406,"journal":{"name":"2008 IEEE International Conference on Semiconductor Electronics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88386832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-09DOI: 10.1109/SMICND.2008.4703424
Mahmoud Zangeneh, H. Aghababa, B. Forouzandeh
This paper presents extracted closed-form expressions for the potential function in cylindrical nanowires in presence of extrinsic charge distribution term, arising from doping. These expressions are derived from the solution to Poisson-Boltzmann ordinary differential equation. This ODE has been solved in terms of intrinsic carrier concentration, temperature and the distance from the central axis of the nanowire in each point inside the wire. Considering extrinsic charge distribution is an innovation in this paper as there assumed to be no external charge in the potential function analysis in previous works. Finally, some simulations have been used to verify the closed-form expressions. These simulations illustrate the potential function of the silicon-based cylindrical nanowire in terms of the distance from its axes and the environmental temperature.
{"title":"Analysis of potential function in cylindrical nanowires","authors":"Mahmoud Zangeneh, H. Aghababa, B. Forouzandeh","doi":"10.1109/SMICND.2008.4703424","DOIUrl":"https://doi.org/10.1109/SMICND.2008.4703424","url":null,"abstract":"This paper presents extracted closed-form expressions for the potential function in cylindrical nanowires in presence of extrinsic charge distribution term, arising from doping. These expressions are derived from the solution to Poisson-Boltzmann ordinary differential equation. This ODE has been solved in terms of intrinsic carrier concentration, temperature and the distance from the central axis of the nanowire in each point inside the wire. Considering extrinsic charge distribution is an innovation in this paper as there assumed to be no external charge in the potential function analysis in previous works. Finally, some simulations have been used to verify the closed-form expressions. These simulations illustrate the potential function of the silicon-based cylindrical nanowire in terms of the distance from its axes and the environmental temperature.","PeriodicalId":6406,"journal":{"name":"2008 IEEE International Conference on Semiconductor Electronics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90757895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-09DOI: 10.1109/SMICND.2008.4703405
I. Sava
The new poly(ester-amide)s were prepared by polycondensation reaction of 1,8-diaminooctane or 1,12-diaminododecane with some diacid chlorides containing preformed ester groups. These polymers were characterized by DSC, polarized light optical microscopy, X-ray diffractions, FTIR and GPC. These polyester-amides show thermotropic liquid crystalline properties and are easily soluble in N-methylpyrrolidinone. The weight average molecular weight is in the range of 2150-3400 and a very closed polydispersity.
{"title":"Liquid-crystalline properties of some poly(ester-amide)s","authors":"I. Sava","doi":"10.1109/SMICND.2008.4703405","DOIUrl":"https://doi.org/10.1109/SMICND.2008.4703405","url":null,"abstract":"The new poly(ester-amide)s were prepared by polycondensation reaction of 1,8-diaminooctane or 1,12-diaminododecane with some diacid chlorides containing preformed ester groups. These polymers were characterized by DSC, polarized light optical microscopy, X-ray diffractions, FTIR and GPC. These polyester-amides show thermotropic liquid crystalline properties and are easily soluble in N-methylpyrrolidinone. The weight average molecular weight is in the range of 2150-3400 and a very closed polydispersity.","PeriodicalId":6406,"journal":{"name":"2008 IEEE International Conference on Semiconductor Electronics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89745058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-01DOI: 10.1109/SMELEC.2008.4770261
V. Arora, M. Tan
After forty years of advances in integrated circuit technology, the scaling of Silicon Metal Oxide Semiconductor Field Effect Transistor (MOSFET) has entered the nanometer dimension with the introduction of 90 nm high volume manufacturing in 2004. Presently at 45 nm going to 32 nm node in 2009, the latest technological advancement has led to low power, high-density and high-speed generation of microprocessors. VLSI circuit and device simulation programs rely heavily on the laws of physics that are being discovered and re-discovered as devices are being scaled down to nanometer regime. The scaling of the Si MOSFET below 22 nm may soon meet its fundamental physical limitations. Nevertheless, novel devices and structures such as graphene, carbon nanotube field effect transistors (CNFETs) and nanowires offer a solution to overcome the performance limits. A clear understanding of a unique electronics and transport properties is vital as simulation programs always lag behind in implementing new findings and parameters that may or may not be physics-based. This paper examines quantum and nonohmic transport phenomena that are capable of predicting the performance of a nanostructure in device and circuit simulations. The ideas presented will allow researchers to identify the input physical processes to form an intelligent perspective in interpreting the output obtained.
{"title":"Quantum nanoelectronics: Challenges and opportunities","authors":"V. Arora, M. Tan","doi":"10.1109/SMELEC.2008.4770261","DOIUrl":"https://doi.org/10.1109/SMELEC.2008.4770261","url":null,"abstract":"After forty years of advances in integrated circuit technology, the scaling of Silicon Metal Oxide Semiconductor Field Effect Transistor (MOSFET) has entered the nanometer dimension with the introduction of 90 nm high volume manufacturing in 2004. Presently at 45 nm going to 32 nm node in 2009, the latest technological advancement has led to low power, high-density and high-speed generation of microprocessors. VLSI circuit and device simulation programs rely heavily on the laws of physics that are being discovered and re-discovered as devices are being scaled down to nanometer regime. The scaling of the Si MOSFET below 22 nm may soon meet its fundamental physical limitations. Nevertheless, novel devices and structures such as graphene, carbon nanotube field effect transistors (CNFETs) and nanowires offer a solution to overcome the performance limits. A clear understanding of a unique electronics and transport properties is vital as simulation programs always lag behind in implementing new findings and parameters that may or may not be physics-based. This paper examines quantum and nonohmic transport phenomena that are capable of predicting the performance of a nanostructure in device and circuit simulations. The ideas presented will allow researchers to identify the input physical processes to form an intelligent perspective in interpreting the output obtained.","PeriodicalId":6406,"journal":{"name":"2008 IEEE International Conference on Semiconductor Electronics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75024899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-25DOI: 10.1109/SMELEC.2008.4770304
Y. Hezarjaribi, M. Hamidon, S. Keshmiri, A. Bahadorimehr
Poly-crystalline silicon carbide (polysic) Micro-electromechanical systems (MEMS) capacitive pressure sensors operating at harsh environments (e.g. high temperature) are proposed because of SiC owing excellent electrical stability, mechanical robustness, and chemical inertness properties. The principle of this paper is, design, simulation. The application of SiC pressure sensors are in a harsh environments such as automotive industries, aerospace, oil/logging equipments, nuclear station, power station. The sensor demonstrated a high temperature sensing capability up to 400degC, the device achieves a linear characteristic response and consists of a circular clamped-edges poly-sic diaphragm suspended over sealed cavity on a silicon carbide substrate. The sensor is operating in touch mode capacitive pressure sensor, The advantages of a touch mode are the robust structure that make the sensor to withstand harsh environment, near linear output, and large over-range protection, operating in wide range of pressure, higher sensitivity than the near linear operation in normal mode, so in this case some of stray capacitance effects can be neglected.
{"title":"Capacitive pressure sensors based on MEMS, operating in harsh environments","authors":"Y. Hezarjaribi, M. Hamidon, S. Keshmiri, A. Bahadorimehr","doi":"10.1109/SMELEC.2008.4770304","DOIUrl":"https://doi.org/10.1109/SMELEC.2008.4770304","url":null,"abstract":"Poly-crystalline silicon carbide (polysic) Micro-electromechanical systems (MEMS) capacitive pressure sensors operating at harsh environments (e.g. high temperature) are proposed because of SiC owing excellent electrical stability, mechanical robustness, and chemical inertness properties. The principle of this paper is, design, simulation. The application of SiC pressure sensors are in a harsh environments such as automotive industries, aerospace, oil/logging equipments, nuclear station, power station. The sensor demonstrated a high temperature sensing capability up to 400degC, the device achieves a linear characteristic response and consists of a circular clamped-edges poly-sic diaphragm suspended over sealed cavity on a silicon carbide substrate. The sensor is operating in touch mode capacitive pressure sensor, The advantages of a touch mode are the robust structure that make the sensor to withstand harsh environment, near linear output, and large over-range protection, operating in wide range of pressure, higher sensitivity than the near linear operation in normal mode, so in this case some of stray capacitance effects can be neglected.","PeriodicalId":6406,"journal":{"name":"2008 IEEE International Conference on Semiconductor Electronics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77665767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/SMELEC.2008.4770409
N. H. Ghazali, H. Soetedjo, N. A. Ngah, A. Yusof, A. Dolah, M. Yahya
In the electronic device fabrication, etching is one of the important processes to do. For this work, the dry etching was done to silicon nitride layer under a CF4 / O2 gas mixture using reactive ion etching (RIE) process has been investigated. This etching process was carried out at a room temperature with gas pressure of 500 mTorr, RF power of 60-80 W, O2 and CF4 flow rate of 5-10 sccm and 40-50 sccm respectively. From the process, a statistical method of Design of Experiment (DOE) Pro XL software was utilized for appropriate analysis.
在电子器件制造中，蚀刻是重要的工艺之一。为此，研究了在CF4 / O2混合气体条件下，采用反应离子刻蚀(RIE)工艺对氮化硅层进行干刻蚀。该刻蚀过程在室温下进行，气体压力为500 mTorr，射频功率为60-80 W, O2和CF4流量分别为5-10 sccm和40-50 sccm。从实验过程来看，利用Design of Experiment (DOE) Pro XL软件的统计方法进行适当的分析。
{"title":"DOE study on etching rate of silicon nitride (Si3N4) layer via RIE nitride etching process","authors":"N. H. Ghazali, H. Soetedjo, N. A. Ngah, A. Yusof, A. Dolah, M. Yahya","doi":"10.1109/SMELEC.2008.4770409","DOIUrl":"https://doi.org/10.1109/SMELEC.2008.4770409","url":null,"abstract":"In the electronic device fabrication, etching is one of the important processes to do. For this work, the dry etching was done to silicon nitride layer under a CF4 / O2 gas mixture using reactive ion etching (RIE) process has been investigated. This etching process was carried out at a room temperature with gas pressure of 500 mTorr, RF power of 60-80 W, O2 and CF4 flow rate of 5-10 sccm and 40-50 sccm respectively. From the process, a statistical method of Design of Experiment (DOE) Pro XL software was utilized for appropriate analysis.","PeriodicalId":6406,"journal":{"name":"2008 IEEE International Conference on Semiconductor Electronics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75147629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/SMELEC.2008.4770353
W. Y. Chiew, S. Binti, A. Radzi
As manufacturers go into volume production with 90 nm designs and below, the floating gate defect (FGD) diagnosis has become a challenge in the initial yield ramp. Since floating gate can result in state-holding, intermittent and pattern-dependent fault effects, these models are generally more complex. Consequently, logical testing is proven can not guarantee the detection of the defect. In this paper, analogue diagnosis to the defect based on defective current is proposed. The magnitude of abnormal increased of power supply current is mainly subjected to the specific location in the Circuit Under Test (CUT), magnitude of input voltage and its sequence. Current open defect diagnosis methods are either keep repeating the circuit simulation based on try and error technique which is tedious or consider part of the factors only for the defect. Thus, the diagnosis results from current procedures may not be as accurate as possible and fully covered. In the proposed method, the significant difference of defective current and the magnitude of voltage supply in sequence are considered using optimization of genetic algorithms (GAs). Results show that the proposed method can achieve a very high diagnosis accuracy and simulation time.
{"title":"Analogue diagnosis of CMOS floating gate defect (FGD) using Genetic Algorithms (GAs)","authors":"W. Y. Chiew, S. Binti, A. Radzi","doi":"10.1109/SMELEC.2008.4770353","DOIUrl":"https://doi.org/10.1109/SMELEC.2008.4770353","url":null,"abstract":"As manufacturers go into volume production with 90 nm designs and below, the floating gate defect (FGD) diagnosis has become a challenge in the initial yield ramp. Since floating gate can result in state-holding, intermittent and pattern-dependent fault effects, these models are generally more complex. Consequently, logical testing is proven can not guarantee the detection of the defect. In this paper, analogue diagnosis to the defect based on defective current is proposed. The magnitude of abnormal increased of power supply current is mainly subjected to the specific location in the Circuit Under Test (CUT), magnitude of input voltage and its sequence. Current open defect diagnosis methods are either keep repeating the circuit simulation based on try and error technique which is tedious or consider part of the factors only for the defect. Thus, the diagnosis results from current procedures may not be as accurate as possible and fully covered. In the proposed method, the significant difference of defective current and the magnitude of voltage supply in sequence are considered using optimization of genetic algorithms (GAs). Results show that the proposed method can achieve a very high diagnosis accuracy and simulation time.","PeriodicalId":6406,"journal":{"name":"2008 IEEE International Conference on Semiconductor Electronics","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74596975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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