Pub Date : 2014-10-30DOI: 10.1109/IIT.2014.6939962
A. G. Lind, K. Jones, C. Hatem
A range of implant temperatures from 20 to 300C are studied for fixed 20 keV implant energy and 6E14 cm-2 dose Si implants into In0.53Ga0.47As. Hall effect measurements performed on the samples after rapid thermal annealing reveal that Si implant activation is actually maximized for intermediate implant temperatures from 50-110C that are shown to be non-amorphizing. While these results echo the conclusion of previous studies that elevated temperature Si implants into In0.53Ga0.47As show increased activation over implants that are likely amorphizing, it is clear that there is a temperature window from 50-110C where activation is improved with increasing thermal budget for the dose and energy studied. Calculated Si solubilities of up to 1.3E19 cm-3 and sheet resistances as low as 26 ohm/sq are achieved for a 10 keV 5E14 cm-2 Si implant performed at 80C after 750C 5s annealing.
{"title":"Activation and defect dissolution of non-amorphizing, elevated temperature Si+ implants into In0.53Ga0.47As","authors":"A. G. Lind, K. Jones, C. Hatem","doi":"10.1109/IIT.2014.6939962","DOIUrl":"https://doi.org/10.1109/IIT.2014.6939962","url":null,"abstract":"A range of implant temperatures from 20 to 300C are studied for fixed 20 keV implant energy and 6E14 cm-2 dose Si implants into In0.53Ga0.47As. Hall effect measurements performed on the samples after rapid thermal annealing reveal that Si implant activation is actually maximized for intermediate implant temperatures from 50-110C that are shown to be non-amorphizing. While these results echo the conclusion of previous studies that elevated temperature Si implants into In0.53Ga0.47As show increased activation over implants that are likely amorphizing, it is clear that there is a temperature window from 50-110C where activation is improved with increasing thermal budget for the dose and energy studied. Calculated Si solubilities of up to 1.3E19 cm-3 and sheet resistances as low as 26 ohm/sq are achieved for a 10 keV 5E14 cm-2 Si implant performed at 80C after 750C 5s annealing.","PeriodicalId":6548,"journal":{"name":"2014 20th International Conference on Ion Implantation Technology (IIT)","volume":"69 3 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2014-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79684422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-30DOI: 10.1109/IIT.2014.6940008
Liping Wang, A. Brown, B. Cheng, A. Asenov
A simulation program, Anadope3D, developed to model ion implantations in FinFETs based on quasi-analytic methods, has been improved to include a set of analytical implantation models based on a Pearson distribution function, which is concise and computationally efficient. This C++ module has been integrated into the GSS atomistic device simulator GARAND, which enables more realistic doping distributions arising from ion implantation to be used for TCAD FinFET simulations. Simulations are performed on an example of an SOI FinFET with physical gate length of 20nm, including statistical simulations with Random Discrete Dopants (RDD). The impact of the realistic 3D doping profile on FinFET performance has been investigated.
{"title":"Simulation of 3D FinFET doping profiles introduced by ion implantation and the impact on device performance","authors":"Liping Wang, A. Brown, B. Cheng, A. Asenov","doi":"10.1109/IIT.2014.6940008","DOIUrl":"https://doi.org/10.1109/IIT.2014.6940008","url":null,"abstract":"A simulation program, Anadope3D, developed to model ion implantations in FinFETs based on quasi-analytic methods, has been improved to include a set of analytical implantation models based on a Pearson distribution function, which is concise and computationally efficient. This C++ module has been integrated into the GSS atomistic device simulator GARAND, which enables more realistic doping distributions arising from ion implantation to be used for TCAD FinFET simulations. Simulations are performed on an example of an SOI FinFET with physical gate length of 20nm, including statistical simulations with Random Discrete Dopants (RDD). The impact of the realistic 3D doping profile on FinFET performance has been investigated.","PeriodicalId":6548,"journal":{"name":"2014 20th International Conference on Ion Implantation Technology (IIT)","volume":"72 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2014-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82393485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-30DOI: 10.1109/IIT.2014.6939954
S. Sharma, W. Aderhold, K. Raman Sharma, A. Mayur
Scaling of semiconductor devices over past decades has been made possible by continuous innovations in materials engineering as well as device integration and geometries. Thermal processing has been an enabler for manufacturing advanced devices, both as a unit process and in concert with other key technologies like ion implantation, epitaxy, and film deposition. This paper reviews the evolution of annealing technology with a special consideration to thermodynamics, kinetics and integration thermal budgets. Equipment and process innovations to meet ever-changing material and device fabrication requirements are presented.
{"title":"Thermal processing for continued scaling of semiconductor devices","authors":"S. Sharma, W. Aderhold, K. Raman Sharma, A. Mayur","doi":"10.1109/IIT.2014.6939954","DOIUrl":"https://doi.org/10.1109/IIT.2014.6939954","url":null,"abstract":"Scaling of semiconductor devices over past decades has been made possible by continuous innovations in materials engineering as well as device integration and geometries. Thermal processing has been an enabler for manufacturing advanced devices, both as a unit process and in concert with other key technologies like ion implantation, epitaxy, and film deposition. This paper reviews the evolution of annealing technology with a special consideration to thermodynamics, kinetics and integration thermal budgets. Equipment and process innovations to meet ever-changing material and device fabrication requirements are presented.","PeriodicalId":6548,"journal":{"name":"2014 20th International Conference on Ion Implantation Technology (IIT)","volume":"1 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2014-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90696872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-30DOI: 10.1109/IIT.2014.6940011
K.-A. Bui-T Meura, F. Torregrosa, A. Robbes, Seo-Youn Choi, A. Merkulov, M. Moret, J. Duchaine, N. Horiguchi, Letian Li, C. Mitterbauer
FinFETs have emerged as a novel transistor architecture for 22nm technology and beyond thanks to good electrostatic control and scalability [1,2]. However, the change from planar to FinFET device architectures challenges the junction formation and the characterization. Fin sidewall doping and doping damages control are critical in scaled FinFETs [3,4,5] but both are difficult to achieve with conventional beamline ion implantation. As an alternative technique, Plasma Immersion Ion implantation (PIII) has shown promising results [6,7]. New characterization techniques such as SIMS through fins, SSRM, atom probe tomography, are needed [8,9,10] to complement standard sheet resistance and SIMS measurements to evaluate sidewall dopants. In this paper we present Low energy Electron X-Ray Emission Spectrometry (LEXES) and SIMS through fins for the characterization of arsenic implants in FinFETs by PIII. STEM-EDX has been used to double check SIMS average data at the fin's scale. The complementarity of these techniques will be presented and excellent conformal fin doping capability of the PULSION® tool is demonstrated.
{"title":"Characterization of arsenic PIII implants in FinFETs by LEXES, SIMS and STEM-EDX","authors":"K.-A. Bui-T Meura, F. Torregrosa, A. Robbes, Seo-Youn Choi, A. Merkulov, M. Moret, J. Duchaine, N. Horiguchi, Letian Li, C. Mitterbauer","doi":"10.1109/IIT.2014.6940011","DOIUrl":"https://doi.org/10.1109/IIT.2014.6940011","url":null,"abstract":"FinFETs have emerged as a novel transistor architecture for 22nm technology and beyond thanks to good electrostatic control and scalability [1,2]. However, the change from planar to FinFET device architectures challenges the junction formation and the characterization. Fin sidewall doping and doping damages control are critical in scaled FinFETs [3,4,5] but both are difficult to achieve with conventional beamline ion implantation. As an alternative technique, Plasma Immersion Ion implantation (PIII) has shown promising results [6,7]. New characterization techniques such as SIMS through fins, SSRM, atom probe tomography, are needed [8,9,10] to complement standard sheet resistance and SIMS measurements to evaluate sidewall dopants. In this paper we present Low energy Electron X-Ray Emission Spectrometry (LEXES) and SIMS through fins for the characterization of arsenic implants in FinFETs by PIII. STEM-EDX has been used to double check SIMS average data at the fin's scale. The complementarity of these techniques will be presented and excellent conformal fin doping capability of the PULSION® tool is demonstrated.","PeriodicalId":6548,"journal":{"name":"2014 20th International Conference on Ion Implantation Technology (IIT)","volume":"6 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2014-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73076424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-30DOI: 10.1109/IIT.2014.6940033
Y. Kato, D. Kimura, K. Yano, S. Kumakura, Y. Imai, T. Nishiokada, F. Sato, T. Iida
A new concept on magnetic field of plasma production and confinement has been proposed to enhance efficiency of an electron cyclotron resonance (ECR) plasma for broad and dense ion beam source under the low pressure. We make this source a part of new tandem type ion source for the first stage. We are also constructing the large bore second stage for synthesizing, extracting and analyzing ions. Both ECR plasmas are necessary to be available to coexist and to be operated individually with different plasma parameters. In the first stage, we optimize the ion beam current and ion saturation current by a mobile plate tuner. They change by the position of the plate tuner for single and multi-frequencies microwaves. The peak positions of them are close to the position where the microwave mode forms standing wave between the plate tuner and the extractor. We show a new guiding principle, which the number of efficiently azimuthal microwave mode should be selected to fit to that of multipole of comb-shaped magnets. We obtained the excitation of selective modes using new mobile plate tuner to enhance ECR efficiency. Furthermore we first obtained charge state distributions of ion beams extracted from the first stage after constructing the second stage and its beam line.
{"title":"Selective microwave mode excitation and charge state distribution on the first stage of tandem type ECRIS","authors":"Y. Kato, D. Kimura, K. Yano, S. Kumakura, Y. Imai, T. Nishiokada, F. Sato, T. Iida","doi":"10.1109/IIT.2014.6940033","DOIUrl":"https://doi.org/10.1109/IIT.2014.6940033","url":null,"abstract":"A new concept on magnetic field of plasma production and confinement has been proposed to enhance efficiency of an electron cyclotron resonance (ECR) plasma for broad and dense ion beam source under the low pressure. We make this source a part of new tandem type ion source for the first stage. We are also constructing the large bore second stage for synthesizing, extracting and analyzing ions. Both ECR plasmas are necessary to be available to coexist and to be operated individually with different plasma parameters. In the first stage, we optimize the ion beam current and ion saturation current by a mobile plate tuner. They change by the position of the plate tuner for single and multi-frequencies microwaves. The peak positions of them are close to the position where the microwave mode forms standing wave between the plate tuner and the extractor. We show a new guiding principle, which the number of efficiently azimuthal microwave mode should be selected to fit to that of multipole of comb-shaped magnets. We obtained the excitation of selective modes using new mobile plate tuner to enhance ECR efficiency. Furthermore we first obtained charge state distributions of ion beams extracted from the first stage after constructing the second stage and its beam line.","PeriodicalId":6548,"journal":{"name":"2014 20th International Conference on Ion Implantation Technology (IIT)","volume":"22 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2014-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90532647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-30DOI: 10.1109/IIT.2014.6940014
G. Margutti, Diego Martirani Paolillo, Marco De Biase, L. Latessa, M. Barozzi, E. Demenev, L. Rubin, C. Spaggiari
In the last years a lot of effort has been directed in order to reduce ion implantation damage, which can be detrimental for silicon device performances. Implantation's dose rate and temperature were found to be two important factors to modulate residual damage left in silicon after anneal. In this work high dose rate, low temperature, high dose arsenic and boron implantations are compared to the corresponding low dose rate, room temperature processes in terms of silicon lattice defectiveness and dopant distribution, before and after anneal is performed. The considered implant processes are the one typically used to form a source/drain region in a CMOS process flow in the submicron technology node. A spike anneal process was applied to activate the dopant. Low temperature, high dose rate implantations have found to be effective in reducing silicon extended defects with a negligible effect on the profile of the activated dopant. Experimental set up, results and possible explanation will be reported and discussed in the paper.
{"title":"Silicon defects characterization for low temperature ion implantation and spike anneal processes","authors":"G. Margutti, Diego Martirani Paolillo, Marco De Biase, L. Latessa, M. Barozzi, E. Demenev, L. Rubin, C. Spaggiari","doi":"10.1109/IIT.2014.6940014","DOIUrl":"https://doi.org/10.1109/IIT.2014.6940014","url":null,"abstract":"In the last years a lot of effort has been directed in order to reduce ion implantation damage, which can be detrimental for silicon device performances. Implantation's dose rate and temperature were found to be two important factors to modulate residual damage left in silicon after anneal. In this work high dose rate, low temperature, high dose arsenic and boron implantations are compared to the corresponding low dose rate, room temperature processes in terms of silicon lattice defectiveness and dopant distribution, before and after anneal is performed. The considered implant processes are the one typically used to form a source/drain region in a CMOS process flow in the submicron technology node. A spike anneal process was applied to activate the dopant. Low temperature, high dose rate implantations have found to be effective in reducing silicon extended defects with a negligible effect on the profile of the activated dopant. Experimental set up, results and possible explanation will be reported and discussed in the paper.","PeriodicalId":6548,"journal":{"name":"2014 20th International Conference on Ion Implantation Technology (IIT)","volume":"85 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2014-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73555470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-30DOI: 10.1109/IIT.2014.6939963
J. Duchaine, F. Torregrosa, Y. Spiegel, G. Borvon, S. Qin, Y. Hu, A. Mcteer
Plasma immersion ion implantation (PIII) technology is known as an alternative to overcome the limitations of conventional beam line ion implantation for shallow, high dose and 3D doping on advanced memory and logic devices. This technique also shows a better CoO as the result of higher productivity, smaller footprint and lower operating costs. Implementation in production for P-type doping and development of N-type applications address issues from the challenges linked to the use of hydrides, especially in the case of AsH3 and PH3. Problems of excessive deposition lead to difficult process integration and possible safety issues such as wafer out-gassing. [1]. Higher priced gases coupled with higher gas consumption compared to beam line are often mentioned as limitations. In this paper we present a full characterization (done at Micron and at IBS) of AsH3 plasma implantation using PULSION® (PIII tool produced by IBS). Due to its unique remote source design, PULSION® allows a wider process window using lower gas flows [2]. These design advantages minimize the before mentioned drawbacks allowing easier process integration [3]. AES (Auger Electron Spectroscopy), ARXPS (Angle Resolution X-ray Photoelectron Spectroscopy), TOF-SIMS & D-SIMS (Secondary Ion Mass Spectrometry), and TEM (Transmission Electron Microscopy) analysis are used to study deposition, doping profiles, and amorphization as a function of acceleration voltage and dose. The effect of dose on sheet resistance after Spike anneal is discussed, as well as the effect of possible hydrogen dilution. Out-gassing measurements are also presented.
{"title":"Study of AsH3 Plasma Immersion Ion Implantation using PULSION®","authors":"J. Duchaine, F. Torregrosa, Y. Spiegel, G. Borvon, S. Qin, Y. Hu, A. Mcteer","doi":"10.1109/IIT.2014.6939963","DOIUrl":"https://doi.org/10.1109/IIT.2014.6939963","url":null,"abstract":"Plasma immersion ion implantation (PIII) technology is known as an alternative to overcome the limitations of conventional beam line ion implantation for shallow, high dose and 3D doping on advanced memory and logic devices. This technique also shows a better CoO as the result of higher productivity, smaller footprint and lower operating costs. Implementation in production for P-type doping and development of N-type applications address issues from the challenges linked to the use of hydrides, especially in the case of AsH3 and PH3. Problems of excessive deposition lead to difficult process integration and possible safety issues such as wafer out-gassing. [1]. Higher priced gases coupled with higher gas consumption compared to beam line are often mentioned as limitations. In this paper we present a full characterization (done at Micron and at IBS) of AsH3 plasma implantation using PULSION® (PIII tool produced by IBS). Due to its unique remote source design, PULSION® allows a wider process window using lower gas flows [2]. These design advantages minimize the before mentioned drawbacks allowing easier process integration [3]. AES (Auger Electron Spectroscopy), ARXPS (Angle Resolution X-ray Photoelectron Spectroscopy), TOF-SIMS & D-SIMS (Secondary Ion Mass Spectrometry), and TEM (Transmission Electron Microscopy) analysis are used to study deposition, doping profiles, and amorphization as a function of acceleration voltage and dose. The effect of dose on sheet resistance after Spike anneal is discussed, as well as the effect of possible hydrogen dilution. Out-gassing measurements are also presented.","PeriodicalId":6548,"journal":{"name":"2014 20th International Conference on Ion Implantation Technology (IIT)","volume":"19 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2014-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76001395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-30DOI: 10.1109/IIT.2014.6940053
S. Simingalam, P. Wijewarnasuriya, M. V. Rao
Arsenic ion-implantation is a standard device processing step to create selective area p+-HgCdTe (MCT) regions in planar devices. One of the issues associated with the ion-implantation process is the significant structural damage to the MCT epilayer. These structural defects limit the performance of diodes via significant tunneling reverse-bias dark currents. After ion-implantation, a high temperature annealing step is required to activate the implant (arsenic) by moving it into the tellurium sublattice and also to heal the lattice damage caused by the implantation process. In this study, we have used thermal cycle annealing (TCA) to decrease ion implantation damage. In TCA, we rapidly heat and cool an MCT sample, which provides an additional degree of freedom that is not obtainable with conventional annealing. We have successfully performed TCA for dislocation defect reduction in in-situ indium-doped MCT with limited inter-diffusion between the absorber layer and cadmium rich cap layer. We also investigated the application of TCA to arsenic ion-implanted MCT. Defects were studied using scanning electron microscopy (SEM) after subjecting the samples to Benson etching to decorate the defects. Mercury-deficient and tellurium-saturated overpressure anneals were performed in an attempt to increase mercury vacancy concentrations and, thereby, increase dislocation climb. Such anneals significantly increased the etch pit density (EPD) in both ion-implanted and un-implanted MCT. By cycle annealing, we have also shown EPD reduction in arsenic ion-implanted, long bar shaped MCT mesas formed on CdTe/Si substrates.
{"title":"Thermal cycle annealing and its application to arsenic-ion implanted HgCdTe","authors":"S. Simingalam, P. Wijewarnasuriya, M. V. Rao","doi":"10.1109/IIT.2014.6940053","DOIUrl":"https://doi.org/10.1109/IIT.2014.6940053","url":null,"abstract":"Arsenic ion-implantation is a standard device processing step to create selective area p+-HgCdTe (MCT) regions in planar devices. One of the issues associated with the ion-implantation process is the significant structural damage to the MCT epilayer. These structural defects limit the performance of diodes via significant tunneling reverse-bias dark currents. After ion-implantation, a high temperature annealing step is required to activate the implant (arsenic) by moving it into the tellurium sublattice and also to heal the lattice damage caused by the implantation process. In this study, we have used thermal cycle annealing (TCA) to decrease ion implantation damage. In TCA, we rapidly heat and cool an MCT sample, which provides an additional degree of freedom that is not obtainable with conventional annealing. We have successfully performed TCA for dislocation defect reduction in in-situ indium-doped MCT with limited inter-diffusion between the absorber layer and cadmium rich cap layer. We also investigated the application of TCA to arsenic ion-implanted MCT. Defects were studied using scanning electron microscopy (SEM) after subjecting the samples to Benson etching to decorate the defects. Mercury-deficient and tellurium-saturated overpressure anneals were performed in an attempt to increase mercury vacancy concentrations and, thereby, increase dislocation climb. Such anneals significantly increased the etch pit density (EPD) in both ion-implanted and un-implanted MCT. By cycle annealing, we have also shown EPD reduction in arsenic ion-implanted, long bar shaped MCT mesas formed on CdTe/Si substrates.","PeriodicalId":6548,"journal":{"name":"2014 20th International Conference on Ion Implantation Technology (IIT)","volume":"13 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2014-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89378761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-30DOI: 10.1109/IIT.2014.6939966
H. Levinson, T. Brunner
Among the challenges with which lithographers are currently grappling, the issues of line-edge roughness (LER) and non-linear overlay errors intersect the concerns of ion implantation and thermal process engineers. LER, and the associated metric for contact holes, local critical dimension uniformity (LCDU), must be small to meet the requirements of advanced nodes. Photon shot-noise-induced LER and LCDU diminution, which can benefit from high resist exposure doses, must be balanced with exposure tool throughput requirements for meeting cost targets for Moore's Law. Because very small improvements in LER and LCDU can require substantial increases in resist exposure doses, post-lithographic techniques for reducing LER and LCDU can have sizable salutary impact on overall wafer costs. The impact of LER on circuit performance depends on the spatial frequencies comprising the LER, and the criticality of particular ranges of spatial frequencies may shift as a consequence of transitions to new types of devices. LER can be reduced post-lithographically by using charged particle beams. Non-linear wafer distortions, which can result from thermal processes and the etching of high-stress films, are problematic for overlay control. Correction of non-linear overlay errors requires the use of a large number of alignment sites and overlay measurements, again resulting in a trade-off between process control and wafer cost. The impact of these distortions on overlay can be predicted quantitatively by measurements of out-of-plane wafer warp. Such measurements can be used to develop processes with intrinsically low distortion and for maintaining process control in manufacturing.
{"title":"Ion beams, thermal processes and lithographic challenges","authors":"H. Levinson, T. Brunner","doi":"10.1109/IIT.2014.6939966","DOIUrl":"https://doi.org/10.1109/IIT.2014.6939966","url":null,"abstract":"Among the challenges with which lithographers are currently grappling, the issues of line-edge roughness (LER) and non-linear overlay errors intersect the concerns of ion implantation and thermal process engineers. LER, and the associated metric for contact holes, local critical dimension uniformity (LCDU), must be small to meet the requirements of advanced nodes. Photon shot-noise-induced LER and LCDU diminution, which can benefit from high resist exposure doses, must be balanced with exposure tool throughput requirements for meeting cost targets for Moore's Law. Because very small improvements in LER and LCDU can require substantial increases in resist exposure doses, post-lithographic techniques for reducing LER and LCDU can have sizable salutary impact on overall wafer costs. The impact of LER on circuit performance depends on the spatial frequencies comprising the LER, and the criticality of particular ranges of spatial frequencies may shift as a consequence of transitions to new types of devices. LER can be reduced post-lithographically by using charged particle beams. Non-linear wafer distortions, which can result from thermal processes and the etching of high-stress films, are problematic for overlay control. Correction of non-linear overlay errors requires the use of a large number of alignment sites and overlay measurements, again resulting in a trade-off between process control and wafer cost. The impact of these distortions on overlay can be predicted quantitatively by measurements of out-of-plane wafer warp. Such measurements can be used to develop processes with intrinsically low distortion and for maintaining process control in manufacturing.","PeriodicalId":6548,"journal":{"name":"2014 20th International Conference on Ion Implantation Technology (IIT)","volume":"40 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2014-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77689770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-30DOI: 10.1109/IIT.2014.6940051
J. Moon, W. Bahng, I. Kang, Sang Cheol Kim, N. Kim
The charge build up in gate oxide and the field effective mobility of 4H-SiC Lateral Double Implanted Metal-Oxide-Semiconductor Field-Effect Transistors (DIMOSFETs) have been evaluated for its dependence on the Post-Oxidation Annealing (POA) time in a nitric oxide gas ambient. NO nitrided oxide for 3 hours significantly reduces the interface trap density near the conduction band and effective oxide charge density, resulting in a decrease of oxide trapped charge in gate oxide during Fowler-Nordheim injection as compared with that of NO POA for 1-2 hours. A high field effect mobility of 11.8 cm2/Vs was successfully achieved in Lateral DIMOSFETs with NO POA for 3 hours. The electrical properties of metal-oxide semiconductor devices fabricated using these oxides are discussed in terms of the oxide's chemical composition.
{"title":"Investigation of charge build-up in NO nitrided gate oxide on 4H-SiC during Fowler-Nordheim injection and fabrication of 4H-SiC Lateral Double-Implanted MOSFETs","authors":"J. Moon, W. Bahng, I. Kang, Sang Cheol Kim, N. Kim","doi":"10.1109/IIT.2014.6940051","DOIUrl":"https://doi.org/10.1109/IIT.2014.6940051","url":null,"abstract":"The charge build up in gate oxide and the field effective mobility of 4H-SiC Lateral Double Implanted Metal-Oxide-Semiconductor Field-Effect Transistors (DIMOSFETs) have been evaluated for its dependence on the Post-Oxidation Annealing (POA) time in a nitric oxide gas ambient. NO nitrided oxide for 3 hours significantly reduces the interface trap density near the conduction band and effective oxide charge density, resulting in a decrease of oxide trapped charge in gate oxide during Fowler-Nordheim injection as compared with that of NO POA for 1-2 hours. A high field effect mobility of 11.8 cm2/Vs was successfully achieved in Lateral DIMOSFETs with NO POA for 3 hours. The electrical properties of metal-oxide semiconductor devices fabricated using these oxides are discussed in terms of the oxide's chemical composition.","PeriodicalId":6548,"journal":{"name":"2014 20th International Conference on Ion Implantation Technology (IIT)","volume":"54 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2014-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83158575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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