Pub Date : 2019-08-01DOI: 10.1109/ICEPT47577.2019.245163
Yang Yang, Xiaole Cui, Yufeng Jin, M. Miao, Huan Liu
In this paper, modeling for TSV pair structures with void defects, pinhole defects and open defects by using an electromagnetic full wave analysis tool is presented. A low-bandwidth equivalent lumped circuit model of above TSV structures are extracted to analyze the effects of different defect sizes and different defect locations. The simulation results show void defects only minimally affect the TSV resistance. And, the lumped circuit model and scattering parameter are changed by open defects which cut off the TSV completely. Besides, the pinhole of a TSV significantly change the equivalent coupling capacitance between TSV pair. Based on these results, some appropriate testing methods are discussed.
{"title":"TSV-defect modeling based electromagnetic full wave analysis and defect diagnosis method design","authors":"Yang Yang, Xiaole Cui, Yufeng Jin, M. Miao, Huan Liu","doi":"10.1109/ICEPT47577.2019.245163","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245163","url":null,"abstract":"In this paper, modeling for TSV pair structures with void defects, pinhole defects and open defects by using an electromagnetic full wave analysis tool is presented. A low-bandwidth equivalent lumped circuit model of above TSV structures are extracted to analyze the effects of different defect sizes and different defect locations. The simulation results show void defects only minimally affect the TSV resistance. And, the lumped circuit model and scattering parameter are changed by open defects which cut off the TSV completely. Besides, the pinhole of a TSV significantly change the equivalent coupling capacitance between TSV pair. Based on these results, some appropriate testing methods are discussed.","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"48 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88421730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/ICEPT47577.2019.245757
Yanning Chen, Shuaipeng Wang, Haifeng Zhang, Dongyan Zhao, Z. Fu, Yidong Yuan, Yubo Wang
Accelerometers are some of the most familiar micro electronic mechanical system (MEMS) sensor. Accelerometers are used in many fields, such as vehicle braking, mobile phone, gauge check and so on. In this paper, we summarize how accelerometers sensors can be operated, and their working principle is presented, and then the fabrication process of the accelerometers sensors is presented. Then we conducted a preliminary test on the performance of the sensor and discuss the optimization scheme of manufacturing process.
{"title":"Design of an accelerometer in inclination monitoring of power transmission pole","authors":"Yanning Chen, Shuaipeng Wang, Haifeng Zhang, Dongyan Zhao, Z. Fu, Yidong Yuan, Yubo Wang","doi":"10.1109/ICEPT47577.2019.245757","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245757","url":null,"abstract":"Accelerometers are some of the most familiar micro electronic mechanical system (MEMS) sensor. Accelerometers are used in many fields, such as vehicle braking, mobile phone, gauge check and so on. In this paper, we summarize how accelerometers sensors can be operated, and their working principle is presented, and then the fabrication process of the accelerometers sensors is presented. Then we conducted a preliminary test on the performance of the sensor and discuss the optimization scheme of manufacturing process.","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"10 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91305151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/ICEPT47577.2019.245184
Qiming Zhang, N. Sinenian, R. Huang
Electrolytic capacitors are of great importance in modern power electronics due to their ability to withstand high voltages for PFC (power factor correction) applications. Solid capacitors, such as ceramic chip capacitors, are not able to achieve this purpose.One of the most common failure modes of electrolytic capacitors is dielectric breakdown, which may lead to internal short-circuits when the capacitor is being charged under high-voltage. Although protection features in the control circuit may be implemented, the voltage fluctuations during the short may still results in failures of other sensitive components in the circuit. Diagnosing such failures is difficult because the functional parameters of the capacitor return to normal following breakdown.One of the dominant reason for dielectric breakdown of electrolytic capacitors is repeated mechanical impact, such as drop loading and vibration, which the jelly-rolled structure of electrolytic capacitors are sensitive to. Repeated mechanical stress may also results in accumulative internal damage to the capacitor and trigger dielectric breakdown over time.The research presented in this paper involves both non-destructive inspection techniques and root cause analysis approaches to analyze typical dielectric breakdown of the capacitor after industry-standard assembly-level drop tests. Based on the failure mode, several measures are proposed to improve the drop reliability of the capacitor in the power electronics. The feasibility of those measures is also analyzed.In summary, we have proposed a potential mitigating strategy to protect power electronics against impact (drop and vibration, etc.) applications, such as high-power portable converters, chargers and electric vehicles
{"title":"Investigations on Electrolytic Capacitors to Improve Reliability under Assembly-Level Impact Conditions","authors":"Qiming Zhang, N. Sinenian, R. Huang","doi":"10.1109/ICEPT47577.2019.245184","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245184","url":null,"abstract":"Electrolytic capacitors are of great importance in modern power electronics due to their ability to withstand high voltages for PFC (power factor correction) applications. Solid capacitors, such as ceramic chip capacitors, are not able to achieve this purpose.One of the most common failure modes of electrolytic capacitors is dielectric breakdown, which may lead to internal short-circuits when the capacitor is being charged under high-voltage. Although protection features in the control circuit may be implemented, the voltage fluctuations during the short may still results in failures of other sensitive components in the circuit. Diagnosing such failures is difficult because the functional parameters of the capacitor return to normal following breakdown.One of the dominant reason for dielectric breakdown of electrolytic capacitors is repeated mechanical impact, such as drop loading and vibration, which the jelly-rolled structure of electrolytic capacitors are sensitive to. Repeated mechanical stress may also results in accumulative internal damage to the capacitor and trigger dielectric breakdown over time.The research presented in this paper involves both non-destructive inspection techniques and root cause analysis approaches to analyze typical dielectric breakdown of the capacitor after industry-standard assembly-level drop tests. Based on the failure mode, several measures are proposed to improve the drop reliability of the capacitor in the power electronics. The feasibility of those measures is also analyzed.In summary, we have proposed a potential mitigating strategy to protect power electronics against impact (drop and vibration, etc.) applications, such as high-power portable converters, chargers and electric vehicles","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"21 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82018778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/ICEPT47577.2019.245239
Jun Li, Ming-chuan Han, Mei Liu, Hangduo Wang, Zhijian Wang
For the past years, acceptance and implementation of copper wire has been become popular and mandatory, especially after gold price soaring for past these years. As compared to gold wire, copper wire poses better electrical conductivity, better thermal conductivity, higher mechanical strength, lower cost and better reliability and so on. But in mass production, we may not be able to achieve desirable performance and manufacturability due to the well-known disadvantages of copper wire. One is its greater hardness, another is being easy to be oxidized. These disadvantages bring challenge to copper wire such as none stick, weak bonding, missing ball, off-center ball, cratering, short tail, smash bond etc.In this paper, off-center ball and 2nd smash bond issue were investigated. a test vehicle with 66um fine pitch and 1.2um bond pad metal thickness was selected as vehicle to study the mechanism of off-center ball and 2nd smash bond issue. First, fish bone analysis was conducted to dig out root cause. Fish bone analysis shows wire tail, EFO current setting and lead frame floating during bonding were suspected to the root cause to the off-center ball and 2nd smash bond. Second, several types of capillary with different OR, tip size and FA were screened. Based on screen result, capillary design was finalized. Second, a DOE was conducted to 2nd bond parameter to resolve off-center ball and 2nd smash bond issue. The factors are 2nd bond force and 2nd bond USG, and 2nd bond scrub offset and phase. Stitch pull strength, 2nd bond width and abnormal 2nd bond shape are responses. 2nd bond parameter was established based on DOE result. Last, EFO parameter DOE was conducted. The factors are EFO time and EFO current. FAB size, FAB roundness and abnormal FAB are responses. Besides, a DOE was conducted to verify 2nd bond parameter. 2nd bond force and 2nd bond USG, and 2nd bond scrub offset are factors, FAB size, FAB roundness, abnormal FAB and stitch pull are responses. EFO parameter window was established based on DOE result. Confirmation run was designed with optimized FAB and 2nd bond parameter. No off-center ball and 2nd smash bond issue were found in high volume production. 2nd bond parameter optimization plays a great role in resolving off-center ball and 2nd smash bond issue.
{"title":"Copper wire off-center ball and 2nd smash bond issue resolution on XQFP package","authors":"Jun Li, Ming-chuan Han, Mei Liu, Hangduo Wang, Zhijian Wang","doi":"10.1109/ICEPT47577.2019.245239","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245239","url":null,"abstract":"For the past years, acceptance and implementation of copper wire has been become popular and mandatory, especially after gold price soaring for past these years. As compared to gold wire, copper wire poses better electrical conductivity, better thermal conductivity, higher mechanical strength, lower cost and better reliability and so on. But in mass production, we may not be able to achieve desirable performance and manufacturability due to the well-known disadvantages of copper wire. One is its greater hardness, another is being easy to be oxidized. These disadvantages bring challenge to copper wire such as none stick, weak bonding, missing ball, off-center ball, cratering, short tail, smash bond etc.In this paper, off-center ball and 2nd smash bond issue were investigated. a test vehicle with 66um fine pitch and 1.2um bond pad metal thickness was selected as vehicle to study the mechanism of off-center ball and 2nd smash bond issue. First, fish bone analysis was conducted to dig out root cause. Fish bone analysis shows wire tail, EFO current setting and lead frame floating during bonding were suspected to the root cause to the off-center ball and 2nd smash bond. Second, several types of capillary with different OR, tip size and FA were screened. Based on screen result, capillary design was finalized. Second, a DOE was conducted to 2nd bond parameter to resolve off-center ball and 2nd smash bond issue. The factors are 2nd bond force and 2nd bond USG, and 2nd bond scrub offset and phase. Stitch pull strength, 2nd bond width and abnormal 2nd bond shape are responses. 2nd bond parameter was established based on DOE result. Last, EFO parameter DOE was conducted. The factors are EFO time and EFO current. FAB size, FAB roundness and abnormal FAB are responses. Besides, a DOE was conducted to verify 2nd bond parameter. 2nd bond force and 2nd bond USG, and 2nd bond scrub offset are factors, FAB size, FAB roundness, abnormal FAB and stitch pull are responses. EFO parameter window was established based on DOE result. Confirmation run was designed with optimized FAB and 2nd bond parameter. No off-center ball and 2nd smash bond issue were found in high volume production. 2nd bond parameter optimization plays a great role in resolving off-center ball and 2nd smash bond issue.","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"58 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79976472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/ICEPT47577.2019.245289
Shengli Ma, Tingting Lian, Han Cai, Liu-lin Hu, Shuwei He
For cooling the 2.5D integrated high power IC device, this paper present a TSV interposer embedded parallel linear microchannels, demonstrate its assembly and thermal property evaluation. The sample is about 9.45 mm 9.5 mm in size, with liner microchannel 100 μm/100 μm in the width/space, 300 μm in the depth, a symmetric flow guiding structure arranged in inlet/outlet region. TSV interposer embedded microchannel is fabricated with DRIE process and Si-Si direct bonding process. For thermal property evaluation, a customized high power IC chip with on site temperature sensor is integrated on the TSV interposer and wired by PCB board. According to the current test results, when the equivalent thermal flux input density is risen to 283 w/cm2, a total thermal input about 66.55 W, the DI wafer is set at a flow rate of 100 ml/min, the temperature rise to 95.1°C, and the pressure drop is 40 Kpa, which is preliminarily verified that it has a good cooling capability.
{"title":"Thermal Property Evaluation of TSV interposer Embedded Microfluidics for Cooling 2.5D Integrated High Power IC Device","authors":"Shengli Ma, Tingting Lian, Han Cai, Liu-lin Hu, Shuwei He","doi":"10.1109/ICEPT47577.2019.245289","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245289","url":null,"abstract":"For cooling the 2.5D integrated high power IC device, this paper present a TSV interposer embedded parallel linear microchannels, demonstrate its assembly and thermal property evaluation. The sample is about 9.45 mm 9.5 mm in size, with liner microchannel 100 μm/100 μm in the width/space, 300 μm in the depth, a symmetric flow guiding structure arranged in inlet/outlet region. TSV interposer embedded microchannel is fabricated with DRIE process and Si-Si direct bonding process. For thermal property evaluation, a customized high power IC chip with on site temperature sensor is integrated on the TSV interposer and wired by PCB board. According to the current test results, when the equivalent thermal flux input density is risen to 283 w/cm2, a total thermal input about 66.55 W, the DI wafer is set at a flow rate of 100 ml/min, the temperature rise to 95.1°C, and the pressure drop is 40 Kpa, which is preliminarily verified that it has a good cooling capability.","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"24 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86544951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The strain distributions in the MLCC during the wave soldering are analyzed with the use of the birth-death element strategy. It is confirmed that the larger size of MLCC is more sensitive to the thermal shock of the wave soldering, while the increased preheating temperature could decrease the principal strain in all the MLCCs. The maximum strain occurs at the junction of the bottom end of the electrode termination and the dielectric ceramics.In compare, the strain distribution in the same size MLCC during the reflow soldering is computed, which indicated smaller principal strain and less thermal shock.
{"title":"Finite-Element Analysis of Strain Distribution in Ceramic Multilayer Capacitors during Wave Soldering and Reflow Soldering","authors":"Hongqin Wang, Wei Li, Dawei Wang, Qingqiu Gong, Jinbao Cai, Sheng-zong He","doi":"10.1109/ICEPT47577.2019.245192","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245192","url":null,"abstract":"The strain distributions in the MLCC during the wave soldering are analyzed with the use of the birth-death element strategy. It is confirmed that the larger size of MLCC is more sensitive to the thermal shock of the wave soldering, while the increased preheating temperature could decrease the principal strain in all the MLCCs. The maximum strain occurs at the junction of the bottom end of the electrode termination and the dielectric ceramics.In compare, the strain distribution in the same size MLCC during the reflow soldering is computed, which indicated smaller principal strain and less thermal shock.","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"5 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82164318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As electronic devices are becoming faster and incorporating more functions, they are simultaneously shrinking in size and weight. These factors suggest significant increases in the packaging densities and heat fluxes for the integrated circuits. Effective thermal management will be the key factor to ensure that these devices perform well with high efficiency and reliability. As the heat dissipation concentrates on tiny gate fingers, the operation of the GaN high-electron mobility transistor (HEMT) posts a huge challenge on thermal management. In order to enhance the heat dissipation capability of GaN power device, it is mostly soldered on the heat spreader with the AuSn solder. However, the thermal conductivity of the AuSn solder is only 57 W•K−1•m−1, which cannot fulfil the reliability requirements of future power electronic devices. New interconnection technologies have to be developed and one of them is a low-temperature pressure-less silver sintering paste with nano silver technology.The joining strength, thermal conduction, electric conductivity and long-term reliability of nano-silver soldering paste under low temperature without pressure are studied, and then compared with AuSn bonder. It forms a strong, highly electrically and thermally conductive bond. Chip shear tests show that 200 °C is already sufficient to generate bonds comparable to solder and high-strength welding interface if the remaining parameters (r, t and T, respectively) are set correctly. However, the strength of the welding interface is only a necessary criterion as chip performance comes into play. Therefore, reliability performance of thermal shock test, high temperature storage test and low temperature storage test are run, which return superior reliability of the sintered samples.In addition, the electrical performance of the GaN power chip is tested. The nano-silver bonded sample is compared with the AuSn sintered sample. The saturated signal output power of these two packaging processes can reach 41dBm, and the leakage current is in the normal range of 0.2A~0.3A. Through reliability test, there is no significant change in these samples, and they all achieve normal electrical performance of the power amplifier component.Besides, thermal performance is one of the important parameters affecting the reliability of high-power devices. In the field of electronic assembly, it is of vital importance to reduce the junction temperature. Ordinary conductive adhesives have lower thermal conductivity which generally below 10 W•K−1•m−1 compared with the AuSn solder. Considering that, it is not suitable to join GaN power devices with the AuSn solder and conductive adhesives. In order to verify the heat dissipation performance of the nano-sintered silver solder samples, 20 samples are prepared for thermal imaging experiments. By observing and comparing the temperature distribution on the surface of nano-silver solder paste sintered chips and the AuSn sintered chips. There are some
{"title":"Reliability of nano-silver soldering paste with high thermal conductivity","authors":"Chunyu Yu, Dongsheng Yang, Donglei Zhao, Zhong Sheng","doi":"10.1109/ICEPT47577.2019.9080930","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.9080930","url":null,"abstract":"As electronic devices are becoming faster and incorporating more functions, they are simultaneously shrinking in size and weight. These factors suggest significant increases in the packaging densities and heat fluxes for the integrated circuits. Effective thermal management will be the key factor to ensure that these devices perform well with high efficiency and reliability. As the heat dissipation concentrates on tiny gate fingers, the operation of the GaN high-electron mobility transistor (HEMT) posts a huge challenge on thermal management. In order to enhance the heat dissipation capability of GaN power device, it is mostly soldered on the heat spreader with the AuSn solder. However, the thermal conductivity of the AuSn solder is only 57 W•K−1•m−1, which cannot fulfil the reliability requirements of future power electronic devices. New interconnection technologies have to be developed and one of them is a low-temperature pressure-less silver sintering paste with nano silver technology.The joining strength, thermal conduction, electric conductivity and long-term reliability of nano-silver soldering paste under low temperature without pressure are studied, and then compared with AuSn bonder. It forms a strong, highly electrically and thermally conductive bond. Chip shear tests show that 200 °C is already sufficient to generate bonds comparable to solder and high-strength welding interface if the remaining parameters (r, t and T, respectively) are set correctly. However, the strength of the welding interface is only a necessary criterion as chip performance comes into play. Therefore, reliability performance of thermal shock test, high temperature storage test and low temperature storage test are run, which return superior reliability of the sintered samples.In addition, the electrical performance of the GaN power chip is tested. The nano-silver bonded sample is compared with the AuSn sintered sample. The saturated signal output power of these two packaging processes can reach 41dBm, and the leakage current is in the normal range of 0.2A~0.3A. Through reliability test, there is no significant change in these samples, and they all achieve normal electrical performance of the power amplifier component.Besides, thermal performance is one of the important parameters affecting the reliability of high-power devices. In the field of electronic assembly, it is of vital importance to reduce the junction temperature. Ordinary conductive adhesives have lower thermal conductivity which generally below 10 W•K−1•m−1 compared with the AuSn solder. Considering that, it is not suitable to join GaN power devices with the AuSn solder and conductive adhesives. In order to verify the heat dissipation performance of the nano-sintered silver solder samples, 20 samples are prepared for thermal imaging experiments. By observing and comparing the temperature distribution on the surface of nano-silver solder paste sintered chips and the AuSn sintered chips. There are some ","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"138 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77459596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Aerospace/airborne military SiP modules have strong demand in high performance, multi-layer flexibility, embedded passive integration and airtightness requirement. Based on this, high-density integrated LTCC (Low Temperature Co-fired Ceramic) based SiP modules with ball grid array (BGA) I/Os show obvious superiority upon other packaging, often being soldered onto Digital/RF printed circuit board (PCB). However, board level ceramic BGA solder joints suffer sustaining random vibration mechanical stress under complicated conditions, for which the interconnection reliability need to be evaluated in advance. In this paper, 3D finite element analysis (FEA) models were developed using ANSYS workbench to understand the vibration-mechanical behavior of CBGA under random vibration test. Related materials properties were accurately obtained by DMA analysis. Simulated load boundaries are consistent with random vibration test bench. The natural frequencies of board level CBGA solder joint LTCC-based SiP specimen were obtained from modal analysis to confirm the vibration mode, based on which the subsequent random vibration simulations were conducted to mapping the equivalent stress/strain distribution of BGAs at interconnect solder joints in X/Y/Z directions. For fatigue prediction, the "three-zone technology" suggested by Steinberg, which taken into consideration both Gaussian distribution and Miner’s linear damage theory together, was used to predict fatigue life of CBGA solder joint under random vibration conditions.
{"title":"Simulation and Fatigue Damage Prediction for Board Level CBGA Solder Joint of LTCC-based SiP Module under Random Vibration Loading","authors":"Yangyang Li, Dong Dong, Hui Wang, Yilong Wu, Le Dong, Rongqing Xu","doi":"10.1109/ICEPT47577.2019.245193","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245193","url":null,"abstract":"Aerospace/airborne military SiP modules have strong demand in high performance, multi-layer flexibility, embedded passive integration and airtightness requirement. Based on this, high-density integrated LTCC (Low Temperature Co-fired Ceramic) based SiP modules with ball grid array (BGA) I/Os show obvious superiority upon other packaging, often being soldered onto Digital/RF printed circuit board (PCB). However, board level ceramic BGA solder joints suffer sustaining random vibration mechanical stress under complicated conditions, for which the interconnection reliability need to be evaluated in advance. In this paper, 3D finite element analysis (FEA) models were developed using ANSYS workbench to understand the vibration-mechanical behavior of CBGA under random vibration test. Related materials properties were accurately obtained by DMA analysis. Simulated load boundaries are consistent with random vibration test bench. The natural frequencies of board level CBGA solder joint LTCC-based SiP specimen were obtained from modal analysis to confirm the vibration mode, based on which the subsequent random vibration simulations were conducted to mapping the equivalent stress/strain distribution of BGAs at interconnect solder joints in X/Y/Z directions. For fatigue prediction, the \"three-zone technology\" suggested by Steinberg, which taken into consideration both Gaussian distribution and Miner’s linear damage theory together, was used to predict fatigue life of CBGA solder joint under random vibration conditions.","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"71 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76603905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/ICEPT47577.2019.246349
Jiake Ma, Yu Wang, Ming Gao, L. Ren, Yifan Huang, R. Sun
In the modern microelectronic devices, one of the most important challenges is efficient removal of heat via thermal interface materials. The interface problem between fillers and polymer is an important issue that restricts the thermal conductivity of thermal interface materials. Herein, we introduce plasma treatment technology to treat the surface of carbon fibers (CFs) to improve the interfacial compatibility between CFs and polymer matrix. The introduced polar oxygen-containing functional groups can promote the intermolecular bonding and the compatibility between the CFs and polymer matrix after the plasma treatment, thereby improving the thermal conductivity of the composites. At the CFs loading of 30 wt%, the CFs/PDMS composites show a better through-plane thermal conductivity (0.43 Wm−1K−1) compared to that of untreated CFs/PDMS composites (0.35 Wm−1K−1). Plasma treatment technology which is environmentally friendly has less damage to fillers and has broad application prospects.
{"title":"Plasma treatment achieving enhanced thermal conductivity of a thermal interface material","authors":"Jiake Ma, Yu Wang, Ming Gao, L. Ren, Yifan Huang, R. Sun","doi":"10.1109/ICEPT47577.2019.246349","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.246349","url":null,"abstract":"In the modern microelectronic devices, one of the most important challenges is efficient removal of heat via thermal interface materials. The interface problem between fillers and polymer is an important issue that restricts the thermal conductivity of thermal interface materials. Herein, we introduce plasma treatment technology to treat the surface of carbon fibers (CFs) to improve the interfacial compatibility between CFs and polymer matrix. The introduced polar oxygen-containing functional groups can promote the intermolecular bonding and the compatibility between the CFs and polymer matrix after the plasma treatment, thereby improving the thermal conductivity of the composites. At the CFs loading of 30 wt%, the CFs/PDMS composites show a better through-plane thermal conductivity (0.43 Wm−1K−1) compared to that of untreated CFs/PDMS composites (0.35 Wm−1K−1). Plasma treatment technology which is environmentally friendly has less damage to fillers and has broad application prospects.","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"103 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79521725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/ICEPT47577.2019.245760
J. Zhuo, Yang Liu, Lishuang Xiong, Yaofang Hu, Liming Gao, Ming Li
With the development of miniaturization of electronic devices, the demand for through-silicon via (TSV) technology has become increasingly urgent. Insulation technology with function of preventing copper diffusion is a key issue for TSV quality and reliability. In this paper, a one-step selective grafting method was reported for covalently grafting polyacrylic acid (PAA) insulation films only on silicon (Si) surface without grafting on aluminum (Al) surface. This method is implemented in an acidic aqueous solution with 4-nitrobenzene diazonium tetrafluoroborate (NBD), hydrofluoric acid (HF), sodium tripolyphosphate (STPP) and acrylic acid (AA) monomers. The existence of STPP in the solution can not only make Si more susceptible to corrosion and further facilitate grafting reaction of PAA films on Si substrate, but also form a layer of sodium fluoroaluminate precipitated film on the Al surface and further avoid the grafting reaction caused by NBD and corrosion of Al by HF. In addition, the effect of surfactants on PAA film formation was studied. Experiments shows that the combination of Sodium dodecyl sulfate (SDS) and sodium lauryl sulfate (SLS) as surfactant can obtain PAA films with great compactness and uniform thickness. This one-step selective grafting method on Si and Al surfaces will have great application prospects for CMOS image sensors (CIS) package when the aspect ratio of TSV increases.
{"title":"A Selective Grafting Method of Polyacrylic Acid Insulation Films on Silicon and Aluminum Surfaces for TSV-CIS Package","authors":"J. Zhuo, Yang Liu, Lishuang Xiong, Yaofang Hu, Liming Gao, Ming Li","doi":"10.1109/ICEPT47577.2019.245760","DOIUrl":"https://doi.org/10.1109/ICEPT47577.2019.245760","url":null,"abstract":"With the development of miniaturization of electronic devices, the demand for through-silicon via (TSV) technology has become increasingly urgent. Insulation technology with function of preventing copper diffusion is a key issue for TSV quality and reliability. In this paper, a one-step selective grafting method was reported for covalently grafting polyacrylic acid (PAA) insulation films only on silicon (Si) surface without grafting on aluminum (Al) surface. This method is implemented in an acidic aqueous solution with 4-nitrobenzene diazonium tetrafluoroborate (NBD), hydrofluoric acid (HF), sodium tripolyphosphate (STPP) and acrylic acid (AA) monomers. The existence of STPP in the solution can not only make Si more susceptible to corrosion and further facilitate grafting reaction of PAA films on Si substrate, but also form a layer of sodium fluoroaluminate precipitated film on the Al surface and further avoid the grafting reaction caused by NBD and corrosion of Al by HF. In addition, the effect of surfactants on PAA film formation was studied. Experiments shows that the combination of Sodium dodecyl sulfate (SDS) and sodium lauryl sulfate (SLS) as surfactant can obtain PAA films with great compactness and uniform thickness. This one-step selective grafting method on Si and Al surfaces will have great application prospects for CMOS image sensors (CIS) package when the aspect ratio of TSV increases.","PeriodicalId":6676,"journal":{"name":"2019 20th International Conference on Electronic Packaging Technology(ICEPT)","volume":"41 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75235923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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