Pub Date : 2017-10-01DOI: 10.23919/EUMIC.2017.8230663
M. Voelkel, M. Dietz, R. Weigel, A. Hagelauer, D. Kissinger
In this paper a 60 GHz monolithic low-power sixport receiver front-end for high precision industrial radar systems is presented. The measurement principle is based on the passive superposition and power detection of two incident millimeter-wave signals. The integrated receiver has been designed using a 0.13 μm SiGe BiCMOS process from IHP (SG13G2) and includes a low noise amplifier (LNA), the passive sixport structure and four detectors. The signal processing in the baseband is done with an ADC-board designed with components from Texas Instruments and a Cyclone IV FPGA board. The integrated receiver circuit has a size of 1320 pm × 950 pm and a low power consumption of 73 mW from a 3.3 V power supply.
{"title":"A low-power 60-GHz integrated sixport receiver front-end in a 130-nm BiCMOS technology","authors":"M. Voelkel, M. Dietz, R. Weigel, A. Hagelauer, D. Kissinger","doi":"10.23919/EUMIC.2017.8230663","DOIUrl":"https://doi.org/10.23919/EUMIC.2017.8230663","url":null,"abstract":"In this paper a 60 GHz monolithic low-power sixport receiver front-end for high precision industrial radar systems is presented. The measurement principle is based on the passive superposition and power detection of two incident millimeter-wave signals. The integrated receiver has been designed using a 0.13 μm SiGe BiCMOS process from IHP (SG13G2) and includes a low noise amplifier (LNA), the passive sixport structure and four detectors. The signal processing in the baseband is done with an ADC-board designed with components from Texas Instruments and a Cyclone IV FPGA board. The integrated receiver circuit has a size of 1320 pm × 950 pm and a low power consumption of 73 mW from a 3.3 V power supply.","PeriodicalId":120932,"journal":{"name":"2017 12th European Microwave Integrated Circuits Conference (EuMIC)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125934011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.23919/EUMIC.2017.8230704
T. Johansen, N. Weimann, R. Doerner, Maruf Hossain, V. Krozer, W. Heinrich
In this paper an electromagnetic (EM) simulation assisted parameters extraction procedure is demonstrated for accurate modeling of down-scaled transferred-substrate InP HBTs. The external parasitic network associated with via transitions and device electrodes is carefully extracted from calibrated 3D EM simulations up to 325 GHz. Following an on-wafer multi-line Through-Reflect-Line (TRL) calibration procedure, the external parasitic network is de-embedded from the transistor measurements and the active device parameters are extracted in a reliable way. The small-signal model structure augmented with the distributed parasitic network is verified against measured S-parameters up to 110 GHz.
{"title":"EM simulation assisted parameter extraction for the modeling of transferred-substrate InP HBTs","authors":"T. Johansen, N. Weimann, R. Doerner, Maruf Hossain, V. Krozer, W. Heinrich","doi":"10.23919/EUMIC.2017.8230704","DOIUrl":"https://doi.org/10.23919/EUMIC.2017.8230704","url":null,"abstract":"In this paper an electromagnetic (EM) simulation assisted parameters extraction procedure is demonstrated for accurate modeling of down-scaled transferred-substrate InP HBTs. The external parasitic network associated with via transitions and device electrodes is carefully extracted from calibrated 3D EM simulations up to 325 GHz. Following an on-wafer multi-line Through-Reflect-Line (TRL) calibration procedure, the external parasitic network is de-embedded from the transistor measurements and the active device parameters are extracted in a reliable way. The small-signal model structure augmented with the distributed parasitic network is verified against measured S-parameters up to 110 GHz.","PeriodicalId":120932,"journal":{"name":"2017 12th European Microwave Integrated Circuits Conference (EuMIC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130170687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.23919/EUMIC.2017.8230674
M. Saeed, A. Hamed, Chun-Yu Fan, Eduard Heidebrecht, R. Negra, M. Shaygan, Zhenxing Wang, D. Neumaier
This paper presents the design, fabrication, and characterization of the first millimeter-wave Graphene-based varactor on flexible substrates. The varactor achieves quality factor better than 10 up to 25 GHz with variation of 5–10% for a bending radius down to 5 mm with pronounced varactor behavior measured up to at least 70 GHz. To prove the substrate independence of the proposed varactor, we fabricated it on high resistivity silicon (HRS) achieving quality factors of 6 at 20 GHz, and on Quartz substrate achieving quality factors of 10 up to 50 GHz. Measurement results promote the proposed varactor for millimeter-Wave circuits and systems applications, especially on flexible substrates.
{"title":"Millimeter-wave graphene-based varactor for flexible electronics","authors":"M. Saeed, A. Hamed, Chun-Yu Fan, Eduard Heidebrecht, R. Negra, M. Shaygan, Zhenxing Wang, D. Neumaier","doi":"10.23919/EUMIC.2017.8230674","DOIUrl":"https://doi.org/10.23919/EUMIC.2017.8230674","url":null,"abstract":"This paper presents the design, fabrication, and characterization of the first millimeter-wave Graphene-based varactor on flexible substrates. The varactor achieves quality factor better than 10 up to 25 GHz with variation of 5–10% for a bending radius down to 5 mm with pronounced varactor behavior measured up to at least 70 GHz. To prove the substrate independence of the proposed varactor, we fabricated it on high resistivity silicon (HRS) achieving quality factors of 6 at 20 GHz, and on Quartz substrate achieving quality factors of 10 up to 50 GHz. Measurement results promote the proposed varactor for millimeter-Wave circuits and systems applications, especially on flexible substrates.","PeriodicalId":120932,"journal":{"name":"2017 12th European Microwave Integrated Circuits Conference (EuMIC)","volume":"306 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115935071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.23919/EUMC.2017.8231020
M. Kucharski, J. Borngraber, Defu Wang, D. Kissinger, H. Ng
This paper presents a 3-stage differential cascode power amplifier (PA) for 109–137 GHz applications. At 120 GHz the circuit delivers 16.5 dBm saturated output power with 12.8 % power-added efficiency (PAE) without using power combining techniques. The chip was fabricated in 130 nm SiGe BiCMOS technology offering heterojunction bipolar transistors (HBT) with fT If max of 300/500 GHz. The PA consists of three stages optimized accordingly to the design goals. The first stage operates in class A to provide high gain while the two following stages are biased in class AB and deep class AB in order to increase the efficiency. The circuit draws a maximum current of 100 mA from 3.3 V and 4 V supplies. It occupies only 0.24 mm2 chip area excluding baluns and bondpads, which makes it attractive for future power combiners. The presented amplifier is suitable for radar applications, that require a high dynamic range.
{"title":"A 109–137 GHz power amplifier in SiGe BiCMOS with 16.5 dBm output power and 12.8% PAE","authors":"M. Kucharski, J. Borngraber, Defu Wang, D. Kissinger, H. Ng","doi":"10.23919/EUMC.2017.8231020","DOIUrl":"https://doi.org/10.23919/EUMC.2017.8231020","url":null,"abstract":"This paper presents a 3-stage differential cascode power amplifier (PA) for 109–137 GHz applications. At 120 GHz the circuit delivers 16.5 dBm saturated output power with 12.8 % power-added efficiency (PAE) without using power combining techniques. The chip was fabricated in 130 nm SiGe BiCMOS technology offering heterojunction bipolar transistors (HBT) with fT If max of 300/500 GHz. The PA consists of three stages optimized accordingly to the design goals. The first stage operates in class A to provide high gain while the two following stages are biased in class AB and deep class AB in order to increase the efficiency. The circuit draws a maximum current of 100 mA from 3.3 V and 4 V supplies. It occupies only 0.24 mm2 chip area excluding baluns and bondpads, which makes it attractive for future power combiners. The presented amplifier is suitable for radar applications, that require a high dynamic range.","PeriodicalId":120932,"journal":{"name":"2017 12th European Microwave Integrated Circuits Conference (EuMIC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126651589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.23919/EUMIC.2017.8230740
Yoji Murao, T. Kaneko
This paper discusses for the first time, to the author's knowledge, the impacts of GaN HEMTs current collapse on memory effects of RF power amplifier at back-off power for high PAPR and wide dynamic range applications. Current collapse induced power gain variation of a 3.5GHz 50W class GaN power amplifier is investigated experimentally within the time scale of nano seconds to micro seconds which is comparative with the sampling interval of the digital predistorter for LTE applications. Combined pulsed and continuous CW signal is used to measure RF gain responses at back-off power and the amount of memory effect is estimated numerically. Measured results are compared with AM-AM of LTE modulated signal and indicate that the current collapse is one of dominating factors of the memory effects of the power amplifier at back-off power.
{"title":"An investigation on current collapse induced memory effects of GaN power amplifier for LTE base station applications","authors":"Yoji Murao, T. Kaneko","doi":"10.23919/EUMIC.2017.8230740","DOIUrl":"https://doi.org/10.23919/EUMIC.2017.8230740","url":null,"abstract":"This paper discusses for the first time, to the author's knowledge, the impacts of GaN HEMTs current collapse on memory effects of RF power amplifier at back-off power for high PAPR and wide dynamic range applications. Current collapse induced power gain variation of a 3.5GHz 50W class GaN power amplifier is investigated experimentally within the time scale of nano seconds to micro seconds which is comparative with the sampling interval of the digital predistorter for LTE applications. Combined pulsed and continuous CW signal is used to measure RF gain responses at back-off power and the amount of memory effect is estimated numerically. Measured results are compared with AM-AM of LTE modulated signal and indicate that the current collapse is one of dominating factors of the memory effects of the power amplifier at back-off power.","PeriodicalId":120932,"journal":{"name":"2017 12th European Microwave Integrated Circuits Conference (EuMIC)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132199025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.23919/EUMIC.2017.8230650
T. Boles
Gallium Nitride, in the form of epitaxial HEMT transistors on silicon carbide substrates is now almost universally acknowledged as the replacement for silicon bipolar, power MOSFET, high power devices in the RF, microwave, and mmW arenas. This is particularly true for GaN-on-SiC based MMIC's which enable state-of-the-art high frequency performance and bandwidth to be extended into Ku-Band and Ka-Band applications. The challenge for GaN-on-Silicon technology is to take advantage of these industry accepted GaN-on-SiC results and leapfrog not only the high frequency/high power performance but also drive GaN into a new cost paradigm, enabling the opening of applications currently beyond the reach of silicon carbide based systems. The design and development of basic GaN-on-Silicon structures and devices will be presented. In this discussion comparisons will be made with alternative substrate materials with emphasis on contrasting the inherent advantages of a silicon based system. Theory of operation of microwave and mmW high power HEMT devices will be presented with special emphasis on fundamental limitations of device performance including limitations on the required impedance transformations, internal and external parasitic reactance, thermal impedance, and optimization, and challenges involved by full integration into monolithic MMICs. Lastly, future directions that will enable the scaling of GaN-on-Silicon production into large wafer diameter, mainstream, CMOS silicon semiconductor technologies and marry CMOS digital control with high power/high frequency devices to create the next generation of monolithic ICs will be discussed.
{"title":"GaN-on-silicon present challenges and future opportunities","authors":"T. Boles","doi":"10.23919/EUMIC.2017.8230650","DOIUrl":"https://doi.org/10.23919/EUMIC.2017.8230650","url":null,"abstract":"Gallium Nitride, in the form of epitaxial HEMT transistors on silicon carbide substrates is now almost universally acknowledged as the replacement for silicon bipolar, power MOSFET, high power devices in the RF, microwave, and mmW arenas. This is particularly true for GaN-on-SiC based MMIC's which enable state-of-the-art high frequency performance and bandwidth to be extended into Ku-Band and Ka-Band applications. The challenge for GaN-on-Silicon technology is to take advantage of these industry accepted GaN-on-SiC results and leapfrog not only the high frequency/high power performance but also drive GaN into a new cost paradigm, enabling the opening of applications currently beyond the reach of silicon carbide based systems. The design and development of basic GaN-on-Silicon structures and devices will be presented. In this discussion comparisons will be made with alternative substrate materials with emphasis on contrasting the inherent advantages of a silicon based system. Theory of operation of microwave and mmW high power HEMT devices will be presented with special emphasis on fundamental limitations of device performance including limitations on the required impedance transformations, internal and external parasitic reactance, thermal impedance, and optimization, and challenges involved by full integration into monolithic MMICs. Lastly, future directions that will enable the scaling of GaN-on-Silicon production into large wafer diameter, mainstream, CMOS silicon semiconductor technologies and marry CMOS digital control with high power/high frequency devices to create the next generation of monolithic ICs will be discussed.","PeriodicalId":120932,"journal":{"name":"2017 12th European Microwave Integrated Circuits Conference (EuMIC)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133926615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.23919/EUMIC.2017.8230700
Arpan Thakkar, Srinivas Theertham, P. Mirajkar, Jagdish Chand Goyal, S. Aniruddhan
A class-C VCO with dual negative feedback architecture is proposed to break the trade-off between amplitude stability of oscillation and bias current flicker noise. Inherent dynamic biasing of this architecture maximizes available voltage swing and provides robust current control without any additional circuits. To inject current exactly at the peak of oscillation, a capacitive feedback technique is proposed which improves phase noise performance further by compensating current injection delay caused due to cross-coupled pair parasitics. This VCO has been implemented in 130nm BiCMOS technology using BJT based cross-coupled pair. It exhibits phase noise performance of −131dBc/Hz @ 1MHz offset when running at 3.9GHz. It exhibits a 14% tuning range, and presents an FoM of 184dBc/Hz.
{"title":"A 3.9–4.5GHz class-C VCO with accurate current injection based on capacitive feedback","authors":"Arpan Thakkar, Srinivas Theertham, P. Mirajkar, Jagdish Chand Goyal, S. Aniruddhan","doi":"10.23919/EUMIC.2017.8230700","DOIUrl":"https://doi.org/10.23919/EUMIC.2017.8230700","url":null,"abstract":"A class-C VCO with dual negative feedback architecture is proposed to break the trade-off between amplitude stability of oscillation and bias current flicker noise. Inherent dynamic biasing of this architecture maximizes available voltage swing and provides robust current control without any additional circuits. To inject current exactly at the peak of oscillation, a capacitive feedback technique is proposed which improves phase noise performance further by compensating current injection delay caused due to cross-coupled pair parasitics. This VCO has been implemented in 130nm BiCMOS technology using BJT based cross-coupled pair. It exhibits phase noise performance of −131dBc/Hz @ 1MHz offset when running at 3.9GHz. It exhibits a 14% tuning range, and presents an FoM of 184dBc/Hz.","PeriodicalId":120932,"journal":{"name":"2017 12th European Microwave Integrated Circuits Conference (EuMIC)","volume":"07 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129329710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.23919/EUMIC.2017.8230711
Efe Öztürk, D. Genschow, U. Yodprasit, Berk Yilmaz, D. Kissinger, W. Debski, W. Winkler
In this paper, a 60 GHz double receive channel FMCW transceiver measurement results together with the design procedure and simulations are presented, considering the license free ISM band. 0.13μm SiGe BiCMOS technology having 250/340 GHz of fr/fmax is utilized to fabricate this fully integrated chip with a die area of 1.65 × 1.05 mm2. The chip is composed of two receiver channels including I/Q based downconverter with a conversion gain and input referred 1dB compression point of 23 dB and −26 dBm respectively at 60 GHz and a transmitter block of over 10 dBm output power combined with a 3-way power divider for the LO signal generated by a 3-bit push-push VCO and a divide-by-32 frequency divider. The total current consumption of this block is 230 mA at 3.3 V of single supply. With the help of three 4-patch on-board antennas designed on a standard high frequency material and I/Q signal processing baseband boards, successful outdoor FMCW system measurements with the proposed transceiver are achieved where obstacles above 70m are detectable.
{"title":"A 60 GHz SiGe BiCMOS double receive channel transceiver for radar applications","authors":"Efe Öztürk, D. Genschow, U. Yodprasit, Berk Yilmaz, D. Kissinger, W. Debski, W. Winkler","doi":"10.23919/EUMIC.2017.8230711","DOIUrl":"https://doi.org/10.23919/EUMIC.2017.8230711","url":null,"abstract":"In this paper, a 60 GHz double receive channel FMCW transceiver measurement results together with the design procedure and simulations are presented, considering the license free ISM band. 0.13μm SiGe BiCMOS technology having 250/340 GHz of fr/fmax is utilized to fabricate this fully integrated chip with a die area of 1.65 × 1.05 mm2. The chip is composed of two receiver channels including I/Q based downconverter with a conversion gain and input referred 1dB compression point of 23 dB and −26 dBm respectively at 60 GHz and a transmitter block of over 10 dBm output power combined with a 3-way power divider for the LO signal generated by a 3-bit push-push VCO and a divide-by-32 frequency divider. The total current consumption of this block is 230 mA at 3.3 V of single supply. With the help of three 4-patch on-board antennas designed on a standard high frequency material and I/Q signal processing baseband boards, successful outdoor FMCW system measurements with the proposed transceiver are achieved where obstacles above 70m are detectable.","PeriodicalId":120932,"journal":{"name":"2017 12th European Microwave Integrated Circuits Conference (EuMIC)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128035149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.23919/EUMIC.2017.8230653
M. Alim, A. Rezazadeh, C. Gaquière
The anomalies and the threshold voltage shifts in GaN and GaAs based high electron mobility transistors over temperature were reported and analyzed using on wafer measurements. Discrepancies are noticed; most conspicuously that the thermal trends of the threshold voltage of the two device technologies are utterly contrasting. This anomaly extends for the other parameters of the devices such as sheet carrier densities of the two-dimension electron gas. In addition barrier inhomogeneities and the band offset of the semiconductor heterojunction with temperature provides some valuable insights between the two competitive device technologies.
{"title":"Anomaly and threshold voltage shifts in GaN and GaAs HEMTs over temperature","authors":"M. Alim, A. Rezazadeh, C. Gaquière","doi":"10.23919/EUMIC.2017.8230653","DOIUrl":"https://doi.org/10.23919/EUMIC.2017.8230653","url":null,"abstract":"The anomalies and the threshold voltage shifts in GaN and GaAs based high electron mobility transistors over temperature were reported and analyzed using on wafer measurements. Discrepancies are noticed; most conspicuously that the thermal trends of the threshold voltage of the two device technologies are utterly contrasting. This anomaly extends for the other parameters of the devices such as sheet carrier densities of the two-dimension electron gas. In addition barrier inhomogeneities and the band offset of the semiconductor heterojunction with temperature provides some valuable insights between the two competitive device technologies.","PeriodicalId":120932,"journal":{"name":"2017 12th European Microwave Integrated Circuits Conference (EuMIC)","volume":"146 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127510007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.23919/EUMIC.2017.8230712
C. Grötsch, A. Tessmann, S. Wagner, I. Kallfass
This paper presents a broadband integrated doublebalanced I/Q-upconverter at 73.5 GHz in a 50 nm InGaAs-based metamorphic high electron mobility transistor technology including Lange couplers with voltage-controlled variable termination resistance. The variable resistance is implemented by using resistive FETs. This MMIC is designed for broadband communication with controllable LO suppression at the output. Introducing Lange couplers with voltage-controlled termination resistance offers a post-production measure to optimize MMICs with respect to I/Q-imbalance and LO isolation. In comparison to conventional 50 Q termination resistances the LO isolation could be improved by up to 12 dB over a bandwidth of 20 GHz while maintaining near constant conversion gain.
{"title":"On-chip post-production tuning of I/Q frequency converters using adjustable coupler terminations","authors":"C. Grötsch, A. Tessmann, S. Wagner, I. Kallfass","doi":"10.23919/EUMIC.2017.8230712","DOIUrl":"https://doi.org/10.23919/EUMIC.2017.8230712","url":null,"abstract":"This paper presents a broadband integrated doublebalanced I/Q-upconverter at 73.5 GHz in a 50 nm InGaAs-based metamorphic high electron mobility transistor technology including Lange couplers with voltage-controlled variable termination resistance. The variable resistance is implemented by using resistive FETs. This MMIC is designed for broadband communication with controllable LO suppression at the output. Introducing Lange couplers with voltage-controlled termination resistance offers a post-production measure to optimize MMICs with respect to I/Q-imbalance and LO isolation. In comparison to conventional 50 Q termination resistances the LO isolation could be improved by up to 12 dB over a bandwidth of 20 GHz while maintaining near constant conversion gain.","PeriodicalId":120932,"journal":{"name":"2017 12th European Microwave Integrated Circuits Conference (EuMIC)","volume":"165 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115041412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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