Pub Date : 2017-10-01DOI: 10.23919/EUMIC.2017.8230730
Lucas Polo‐López, J. Masa-Campos, J. Ruiz‐Cruz
In this work the design of a Ku-band reconfigurable phase shifter implemented in waveguide technology is presented. The reconfiguration capability of the device is achieved by the insertion of a pair of adjustable metallic posts. A prototype of this device has been manufactured using a 3D printing technique in order to show the proposed concept. The measured return loss and phase performances of this prototype are compared with the simulated full-wave response of the phase shifter. The proposed waveguide component shows a great application potential in the area of beam steering phased arrays implemented in waveguide technology, since the presented phase shifter is fully developed in waveguide, not requiring the additional transitions to planar structures usually needed to integrate lumped components.
{"title":"Design of a reconfigurable rectangular waveguide phase shifter with metallic posts","authors":"Lucas Polo‐López, J. Masa-Campos, J. Ruiz‐Cruz","doi":"10.23919/EUMIC.2017.8230730","DOIUrl":"https://doi.org/10.23919/EUMIC.2017.8230730","url":null,"abstract":"In this work the design of a Ku-band reconfigurable phase shifter implemented in waveguide technology is presented. The reconfiguration capability of the device is achieved by the insertion of a pair of adjustable metallic posts. A prototype of this device has been manufactured using a 3D printing technique in order to show the proposed concept. The measured return loss and phase performances of this prototype are compared with the simulated full-wave response of the phase shifter. The proposed waveguide component shows a great application potential in the area of beam steering phased arrays implemented in waveguide technology, since the presented phase shifter is fully developed in waveguide, not requiring the additional transitions to planar structures usually needed to integrate lumped components.","PeriodicalId":120932,"journal":{"name":"2017 12th European Microwave Integrated Circuits Conference (EuMIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129567410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.23919/eumic.2017.8230713
M. Bao, Z. He, H. Zirath
A 6-stage, 8-way combining power amplifier (PA) in a 130 nm SiGe BiCMOS technology is designed and measured. This PA has an output power of 12.5–15.5 dBm in a frequency range from 100 GHz to 145 GHz, when the input power is about 2 dBm. The small signal gain is 19 dB and the maximum DC power consumption is 480 mW with a supply voltage of 1.87 V. The peak power added efficiency (PAE) is 6.4% in D-band. T-junctions are utilized to combine and divide millimeter-wave power. To reduce the PA's loss and chip area, neither a Wilkinson power combiner/divider nor a balun is applied. The chip size is 0.53 mm2 (0.26 mm2 without pads).
{"title":"A 100–145 GHz area-efficient power amplifier in a 130 nm SiGe technology","authors":"M. Bao, Z. He, H. Zirath","doi":"10.23919/eumic.2017.8230713","DOIUrl":"https://doi.org/10.23919/eumic.2017.8230713","url":null,"abstract":"A 6-stage, 8-way combining power amplifier (PA) in a 130 nm SiGe BiCMOS technology is designed and measured. This PA has an output power of 12.5–15.5 dBm in a frequency range from 100 GHz to 145 GHz, when the input power is about 2 dBm. The small signal gain is 19 dB and the maximum DC power consumption is 480 mW with a supply voltage of 1.87 V. The peak power added efficiency (PAE) is 6.4% in D-band. T-junctions are utilized to combine and divide millimeter-wave power. To reduce the PA's loss and chip area, neither a Wilkinson power combiner/divider nor a balun is applied. The chip size is 0.53 mm2 (0.26 mm2 without pads).","PeriodicalId":120932,"journal":{"name":"2017 12th European Microwave Integrated Circuits Conference (EuMIC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128349629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.23919/EUMIC.2017.8230732
H. Tao, W. Hong, Bin Zhang
The design and performance of a compact 6–18GHz power amplifier MMIC utilizing 0.2 pm gallium nitride (GaN) high electron mobility transistor (HEMT) technology is presented. An output power of 41.4 dBm to 43.3 dBm (average 42.3dBm) with over 16 dB power gain and a power added efficiency (PAE) of 21% to 35% over the band of 6–18 GHz under a drain voltage of 28 V in CW mode have been achieved. The chip size is compact with the size of 2.6∗3.6 mm2 and it delivers an average output power density 1.83 W/mm2 over the chip area. The thermal resistance is 1.55 T7W measured in CW mode.
{"title":"6–18GHz 13W reactive matched GaN power amplifier MMIC","authors":"H. Tao, W. Hong, Bin Zhang","doi":"10.23919/EUMIC.2017.8230732","DOIUrl":"https://doi.org/10.23919/EUMIC.2017.8230732","url":null,"abstract":"The design and performance of a compact 6–18GHz power amplifier MMIC utilizing 0.2 pm gallium nitride (GaN) high electron mobility transistor (HEMT) technology is presented. An output power of 41.4 dBm to 43.3 dBm (average 42.3dBm) with over 16 dB power gain and a power added efficiency (PAE) of 21% to 35% over the band of 6–18 GHz under a drain voltage of 28 V in CW mode have been achieved. The chip size is compact with the size of 2.6∗3.6 mm2 and it delivers an average output power density 1.83 W/mm2 over the chip area. The thermal resistance is 1.55 T7W measured in CW mode.","PeriodicalId":120932,"journal":{"name":"2017 12th European Microwave Integrated Circuits Conference (EuMIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130672513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.23919/EUMIC.2017.8230664
J. Moody, Pouyan Bassirian, Abhishek Roy, Yukang Feng, Shuo Li, R. Costanzo, N. S. Barker, B. Calhoun, S. Bowers
This work presents an ultra-low power event driven wake-up receiver (WuRx) fabricated in a RF CMOS 130 nm process. The receiver consists of an off-chip lumped element matching network, an envelope detector, a decision circuit capable of detecting sub-mV baseband signal voltages and a clock source consuming 1.3 nW. This receiver has demonstrated a sensitivity of −72 dBm while consuming a total of 8.3 nW from 1 V and 0.65 V sources.
{"title":"An 8.3 nW −72 dBm event driven IoE wake up receiver RF front end","authors":"J. Moody, Pouyan Bassirian, Abhishek Roy, Yukang Feng, Shuo Li, R. Costanzo, N. S. Barker, B. Calhoun, S. Bowers","doi":"10.23919/EUMIC.2017.8230664","DOIUrl":"https://doi.org/10.23919/EUMIC.2017.8230664","url":null,"abstract":"This work presents an ultra-low power event driven wake-up receiver (WuRx) fabricated in a RF CMOS 130 nm process. The receiver consists of an off-chip lumped element matching network, an envelope detector, a decision circuit capable of detecting sub-mV baseband signal voltages and a clock source consuming 1.3 nW. This receiver has demonstrated a sensitivity of −72 dBm while consuming a total of 8.3 nW from 1 V and 0.65 V sources.","PeriodicalId":120932,"journal":{"name":"2017 12th European Microwave Integrated Circuits Conference (EuMIC)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122904869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.23919/EUMIC.2017.8230733
Ru-Yu Wang, Sen Wang
In this paper, a low-loss and high-selectivity compact CMOS bandpass filter at S band is presented. The filter based on lumped elements achieves low insertion loss and ultrawide bandwidth. Moreover, the resonators of the filter result in two finite transmission zeros. One transmission zero is in the lower stopband, and the other is in the upper stopband, thus improving the selectivity of the filter significantly. The filter is designed and fabricated in a standard 0.18-μm CMOS technology with a chip area of 745 mm × 790 mm including all testing pads. The filter achieves 2.7-dB insertion loss and 64% 3-dB bandwidth at 2.5 GHz. Measured results also show that the two transmission zeros are at 1.1 GHz and 4.8 GHz featuring 26.6-dB and 44.5-dB rejection, respectively.
{"title":"Low-loss and compact 2.4-GHz CMOS bandpass filter with finite transmission zeros","authors":"Ru-Yu Wang, Sen Wang","doi":"10.23919/EUMIC.2017.8230733","DOIUrl":"https://doi.org/10.23919/EUMIC.2017.8230733","url":null,"abstract":"In this paper, a low-loss and high-selectivity compact CMOS bandpass filter at S band is presented. The filter based on lumped elements achieves low insertion loss and ultrawide bandwidth. Moreover, the resonators of the filter result in two finite transmission zeros. One transmission zero is in the lower stopband, and the other is in the upper stopband, thus improving the selectivity of the filter significantly. The filter is designed and fabricated in a standard 0.18-μm CMOS technology with a chip area of 745 mm × 790 mm including all testing pads. The filter achieves 2.7-dB insertion loss and 64% 3-dB bandwidth at 2.5 GHz. Measured results also show that the two transmission zeros are at 1.1 GHz and 4.8 GHz featuring 26.6-dB and 44.5-dB rejection, respectively.","PeriodicalId":120932,"journal":{"name":"2017 12th European Microwave Integrated Circuits Conference (EuMIC)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126337789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.23919/EUMIC.2017.8230655
P. Schuh, H. Sledzik, R. Reber
A next generation of AESA antennas will be challenged with the need for lower size, weight, power and cost (SWAP-C). This leads to enhanced demands especially with regard to the integration density of the RF-part inside a T/R module. The semiconductor material GaN has proven its capacity for high power amplifiers, robust receive components as well as switch components for separation of transmit and receive mode. This paper will describe the design and measurement results of a GaN-based single-chip T/R module frontend (HPA, LNA and SPDT) using UMS GH25 technology and covering the frequency range from 8 GHz to 12 GHz. Key performance parameters of the frontend are 13 W minimum transmit (TX) output power over the whole frequency range with peak power up to 17 W. The frontend in receive (RX) mode has a noise figure below 3.2 dB over the whole frequency range, and can survive more than 5 W input power. The large signal insertion loss of the used SPDT is below 0.9 dB at 43 dBm input power level.
{"title":"High performance GaN single-chip frontend for compact X-band AESA systems","authors":"P. Schuh, H. Sledzik, R. Reber","doi":"10.23919/EUMIC.2017.8230655","DOIUrl":"https://doi.org/10.23919/EUMIC.2017.8230655","url":null,"abstract":"A next generation of AESA antennas will be challenged with the need for lower size, weight, power and cost (SWAP-C). This leads to enhanced demands especially with regard to the integration density of the RF-part inside a T/R module. The semiconductor material GaN has proven its capacity for high power amplifiers, robust receive components as well as switch components for separation of transmit and receive mode. This paper will describe the design and measurement results of a GaN-based single-chip T/R module frontend (HPA, LNA and SPDT) using UMS GH25 technology and covering the frequency range from 8 GHz to 12 GHz. Key performance parameters of the frontend are 13 W minimum transmit (TX) output power over the whole frequency range with peak power up to 17 W. The frontend in receive (RX) mode has a noise figure below 3.2 dB over the whole frequency range, and can survive more than 5 W input power. The large signal insertion loss of the used SPDT is below 0.9 dB at 43 dBm input power level.","PeriodicalId":120932,"journal":{"name":"2017 12th European Microwave Integrated Circuits Conference (EuMIC)","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124010102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.23919/EUMIC.2017.8230693
S. Maroldt, M. Ercoli
This paper presents a high gain ultra-compact Doherty PA design approach based on 28 V two-stage GaN MMICs. A 20 W asymmetric and 26 W symmetric Doherty amplifier operating in the 3.4–3.6 GHz band were designed into a small footprint 7×7 mm2 QFN plastic package for 5G massive MIMO base station applications. The use of package-integrated low-loss passive devices to realize the class-E like inverted Doherty combiner resulted in excellent final stage drain efficiencies of 60 % at 8 dB output power back-off and 65 % in saturation, to the best of the authors' knowledge the highest reported final stage drain efficiency for GaN MMIC based integrated Doherty PAs in the 3.5 GHz band. The full asymmetric PA board yields a measured line-up efficiency of 43 % with an associated gain of 26 dB at 35 dBm average power of a 20 MHz LTE signal, corresponding to 8 dB output power back-off.
{"title":"3.5-GHz ultra-compact GaN class-E integrated Doherty MMIC PA for 5G massive-MIMO base station applications","authors":"S. Maroldt, M. Ercoli","doi":"10.23919/EUMIC.2017.8230693","DOIUrl":"https://doi.org/10.23919/EUMIC.2017.8230693","url":null,"abstract":"This paper presents a high gain ultra-compact Doherty PA design approach based on 28 V two-stage GaN MMICs. A 20 W asymmetric and 26 W symmetric Doherty amplifier operating in the 3.4–3.6 GHz band were designed into a small footprint 7×7 mm2 QFN plastic package for 5G massive MIMO base station applications. The use of package-integrated low-loss passive devices to realize the class-E like inverted Doherty combiner resulted in excellent final stage drain efficiencies of 60 % at 8 dB output power back-off and 65 % in saturation, to the best of the authors' knowledge the highest reported final stage drain efficiency for GaN MMIC based integrated Doherty PAs in the 3.5 GHz band. The full asymmetric PA board yields a measured line-up efficiency of 43 % with an associated gain of 26 dB at 35 dBm average power of a 20 MHz LTE signal, corresponding to 8 dB output power back-off.","PeriodicalId":120932,"journal":{"name":"2017 12th European Microwave Integrated Circuits Conference (EuMIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122472371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.23919/EUMIC.2017.8230701
Abdel Martinez Alonso, Xia Yuan, M. Miyahara, A. Matsuzawa
This paper describes a Digital-Mapping Direct Digital Frequency Synthesizer consuming only 118 mW when operating at 2 GS/s in 65nm CMOS. The active area is 0.142 mm2 with an accumulator size and amplitude resolution of 24 and 10 bits respectively. The Spurious-Free Dynamic Range is better than 41 dBc for synthesized frequencies below 750 MHz and 30 dBc over the entire Nyquist bandwidth. The Power Efficiency reaches 59 mW/(GS/s) by implementing a Complementary DualPhase Latch-Based architecture. Prototypes encapsulated in a 144-pin Low-Profile Quad Flat Package were employed during measurements. The achieved FoM is 542 GS/s • 2(SFDR/6)/W.
{"title":"A 2 GS/s 118 mW digital-mapping direct digital frequency synthesizer in 65nm CMOS","authors":"Abdel Martinez Alonso, Xia Yuan, M. Miyahara, A. Matsuzawa","doi":"10.23919/EUMIC.2017.8230701","DOIUrl":"https://doi.org/10.23919/EUMIC.2017.8230701","url":null,"abstract":"This paper describes a Digital-Mapping Direct Digital Frequency Synthesizer consuming only 118 mW when operating at 2 GS/s in 65nm CMOS. The active area is 0.142 mm2 with an accumulator size and amplitude resolution of 24 and 10 bits respectively. The Spurious-Free Dynamic Range is better than 41 dBc for synthesized frequencies below 750 MHz and 30 dBc over the entire Nyquist bandwidth. The Power Efficiency reaches 59 mW/(GS/s) by implementing a Complementary DualPhase Latch-Based architecture. Prototypes encapsulated in a 144-pin Low-Profile Quad Flat Package were employed during measurements. The achieved FoM is 542 GS/s • 2(SFDR/6)/W.","PeriodicalId":120932,"journal":{"name":"2017 12th European Microwave Integrated Circuits Conference (EuMIC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115198561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.23919/EUMIC.2017.8230703
F. Herzel, M. Kucharski, A. Ergintav, J. Borngräber, H. Ng, J. Domke, D. Kissinger
An integrated frequency synthesizer for 28.733.7 GHz is presented. This wide tuning range is achieved at low phase noise by combining capacitive tuning and inductor switching in the voltage-controlled oscillator (VCO). The synthesizer lends itself to the realization of integrated transceiver frontends when using a sliding-IF architecture, both for the 28 GHz and the 38 GHz band. It occupies a chip area of 5 mm2 including bondpads and draws 171 mA from a 2.5 V supply. The phase noise at 1 MHz offset from the 30 GHz carrier is between −100 and −97 dBc/Hz.
{"title":"An integrated frequency synthesizer in 130 nm SiGe BiCMOS technology for 28/38 GHz 5G wireless networks","authors":"F. Herzel, M. Kucharski, A. Ergintav, J. Borngräber, H. Ng, J. Domke, D. Kissinger","doi":"10.23919/EUMIC.2017.8230703","DOIUrl":"https://doi.org/10.23919/EUMIC.2017.8230703","url":null,"abstract":"An integrated frequency synthesizer for 28.733.7 GHz is presented. This wide tuning range is achieved at low phase noise by combining capacitive tuning and inductor switching in the voltage-controlled oscillator (VCO). The synthesizer lends itself to the realization of integrated transceiver frontends when using a sliding-IF architecture, both for the 28 GHz and the 38 GHz band. It occupies a chip area of 5 mm2 including bondpads and draws 171 mA from a 2.5 V supply. The phase noise at 1 MHz offset from the 30 GHz carrier is between −100 and −97 dBc/Hz.","PeriodicalId":120932,"journal":{"name":"2017 12th European Microwave Integrated Circuits Conference (EuMIC)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127139112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.23919/EUMIC.2017.8230691
M. Acar, O. Ceylan, Felicia Kiebler, S. Pires, S. Maroldt
In this paper, we show that low-voltage operation of a GaN transistor (5.5V) as a driver allows very high line-up efficiency, including driver and end-stage. We realized two-stage MMIC in 0.25pm GaN HEMT technology. The MMIC die and high harmonic matching circuits were assembled into a standard ceramic RF package. The load-pull measurement results of the packaged MMIC show that the line-up efficiency is preserved to >70% in the presence of an 8 dB output power variation. We designed a PCB based on the load-pull measurement data as a demonstration board. We measured 76% line-up efficiency with an output power of 35.4dBm and a linear gain of 27dB at 2.14 GHz. Applying a WCDMA signal, a −52.4dBc ACLR performance was observed at 29.4dBm average output power using a vector switched generalized memory polynomial digital pre-distortion (VS-GMP DPD) algorithm.
在本文中，我们展示了GaN晶体管(5.5V)作为驱动器的低压操作可以实现非常高的排列效率，包括驱动器和终端级。我们在0.25pm GaN HEMT技术中实现了两级MMIC。MMIC芯片和高谐波匹配电路被组装成一个标准的陶瓷射频封装。封装MMIC的负载-拉力测量结果表明，在8 dB输出功率变化的情况下，线路效率保持在>70%。我们根据负载-拉力测量数据设计了一个PCB作为演示板。我们在2.14 GHz时测量了76%的线路效率，输出功率为35.4dBm，线性增益为27dB。应用WCDMA信号，采用矢量开关广义记忆多项式数字预失真(VS-GMP DPD)算法，在29.4dBm平均输出功率下，ACLR性能为- 52.4dBc。
{"title":"Highly efficient GaN RF power amplifier MMIC using low-voltage driver","authors":"M. Acar, O. Ceylan, Felicia Kiebler, S. Pires, S. Maroldt","doi":"10.23919/EUMIC.2017.8230691","DOIUrl":"https://doi.org/10.23919/EUMIC.2017.8230691","url":null,"abstract":"In this paper, we show that low-voltage operation of a GaN transistor (5.5V) as a driver allows very high line-up efficiency, including driver and end-stage. We realized two-stage MMIC in 0.25pm GaN HEMT technology. The MMIC die and high harmonic matching circuits were assembled into a standard ceramic RF package. The load-pull measurement results of the packaged MMIC show that the line-up efficiency is preserved to >70% in the presence of an 8 dB output power variation. We designed a PCB based on the load-pull measurement data as a demonstration board. We measured 76% line-up efficiency with an output power of 35.4dBm and a linear gain of 27dB at 2.14 GHz. Applying a WCDMA signal, a −52.4dBc ACLR performance was observed at 29.4dBm average output power using a vector switched generalized memory polynomial digital pre-distortion (VS-GMP DPD) algorithm.","PeriodicalId":120932,"journal":{"name":"2017 12th European Microwave Integrated Circuits Conference (EuMIC)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126278064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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