Pub Date : 2017-10-01DOI: 10.23919/EUMIC.2017.8230648
Saad Qayyum, R. Negra
This paper presents the design and implementation of a low power, wideband and high sensitivity CMOS power detector in 130 nm standard CMOS technology. It utilises a travelling-wave structure to achieve wideband input matching bandwidth from 7 GHz to more than 70 GHz. By biasing the power detectors in subthreshold regime, it achieves a measured peak voltage sensitivity of 75 dB at 7 GHz while maintaining more than 67 dB from 100 MHz up to 70 GHz. The DC power consumption of the proposed design is 0.156 mW from 1.2 V supply. The total area of the power detector is 380 μm × 180 μm, excluding pads.
{"title":"0.16 mW, 7–70 GHz distributed power detector with 75 dB voltage sensitivity in 130 nm standard CMOS technology","authors":"Saad Qayyum, R. Negra","doi":"10.23919/EUMIC.2017.8230648","DOIUrl":"https://doi.org/10.23919/EUMIC.2017.8230648","url":null,"abstract":"This paper presents the design and implementation of a low power, wideband and high sensitivity CMOS power detector in 130 nm standard CMOS technology. It utilises a travelling-wave structure to achieve wideband input matching bandwidth from 7 GHz to more than 70 GHz. By biasing the power detectors in subthreshold regime, it achieves a measured peak voltage sensitivity of 75 dB at 7 GHz while maintaining more than 67 dB from 100 MHz up to 70 GHz. The DC power consumption of the proposed design is 0.156 mW from 1.2 V supply. The total area of the power detector is 380 μm × 180 μm, excluding pads.","PeriodicalId":120932,"journal":{"name":"2017 12th European Microwave Integrated Circuits Conference (EuMIC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131732506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.23919/EUMIC.2017.8230696
J. King, C. Wilson
The paper presents a comprehensive charge modelling approach for field-effect transistor (FET) devices. For the first time an artificial neural network (ANN) is combined with the division-by-current approach to FET charge modelling. Using this technique a large-signal charge model is extracted for a 10 W GaN device from MACOM. It is shown through measurements that excellent results may be obtained using just a single gate charge function, integrated analytically from small-signal measurements.
{"title":"Charge conservative FET modelling using ANNs","authors":"J. King, C. Wilson","doi":"10.23919/EUMIC.2017.8230696","DOIUrl":"https://doi.org/10.23919/EUMIC.2017.8230696","url":null,"abstract":"The paper presents a comprehensive charge modelling approach for field-effect transistor (FET) devices. For the first time an artificial neural network (ANN) is combined with the division-by-current approach to FET charge modelling. Using this technique a large-signal charge model is extracted for a 10 W GaN device from MACOM. It is shown through measurements that excellent results may be obtained using just a single gate charge function, integrated analytically from small-signal measurements.","PeriodicalId":120932,"journal":{"name":"2017 12th European Microwave Integrated Circuits Conference (EuMIC)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127236176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.23919/EUMIC.2017.8230692
T. Quach, P. Watson, B. Dupaix, T. Barton, M. LaRue, W. Gouty, W. Khalil
This work presents a wideband digital PA topology implemented in Gallium Nitride MMIC for a direct-digital RF transmitter. The topology employs a differential current mode driver and GaN inverter stage with active pull-up to drive an efficient switch-mode PA. By applying digital circuit design techniques in GaN, our approach enables wide-band digital drive of a switched-mode PA through pulse-width and pulse-position control. The approach is experimentally validated in a 0.2 pm GaN on SiC foundry process at C band. The digital PA operates over a 2.5–6.0 GHz range with total drain efficiency greater than 30%, final-stage drain efficiency yielded over 40%, and peak output power of 35.2 dBm.
这项工作提出了一个宽带数字PA拓扑实现在氮化镓MMIC直接数字射频发射机。该拓扑结构采用差分电流模式驱动器和具有有源上拉的GaN逆变级来驱动高效的开关模式PA。通过在GaN中应用数字电路设计技术，我们的方法通过脉冲宽度和脉冲位置控制实现了开关模式PA的宽带数字驱动。该方法在C波段的0.2 pm GaN - SiC铸造工艺中得到了实验验证。数字放大器工作在2.5-6.0 GHz范围内，总漏极效率大于30%，末级漏极效率超过40%，峰值输出功率为35.2 dBm。
{"title":"Wideband high-efficiency digital power amplifier in GaN","authors":"T. Quach, P. Watson, B. Dupaix, T. Barton, M. LaRue, W. Gouty, W. Khalil","doi":"10.23919/EUMIC.2017.8230692","DOIUrl":"https://doi.org/10.23919/EUMIC.2017.8230692","url":null,"abstract":"This work presents a wideband digital PA topology implemented in Gallium Nitride MMIC for a direct-digital RF transmitter. The topology employs a differential current mode driver and GaN inverter stage with active pull-up to drive an efficient switch-mode PA. By applying digital circuit design techniques in GaN, our approach enables wide-band digital drive of a switched-mode PA through pulse-width and pulse-position control. The approach is experimentally validated in a 0.2 pm GaN on SiC foundry process at C band. The digital PA operates over a 2.5–6.0 GHz range with total drain efficiency greater than 30%, final-stage drain efficiency yielded over 40%, and peak output power of 35.2 dBm.","PeriodicalId":120932,"journal":{"name":"2017 12th European Microwave Integrated Circuits Conference (EuMIC)","volume":"595 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115856853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.23919/EUMIC.2017.8230652
I. Khalil, H. Rueda, Damon Holmes, P. Chakraborty, D. Burdeaux
A modeling method for RF power transistor fingers and large discrete die is presented in order to evaluate, visualize, and optimize various performance parameters at the device finger level. The model is constructed using a combination of TCAD based active die model and passive interconnect models based on Wheeler's transmission line formulation. Active die model of a fraction of the total periphery are connected with the interconnect models to build arbitrarily sized RF power transistors. The advantage of such model is shown to be flexibility of probing different parameters (e.g. voltage, current) at distinct die locations. Additionally, interconnect of the power transistor can be optimized in the simulation space in order to realize improved performance.
{"title":"TCAD based segmented modelling of large RF power-transistors-die for finger level analysis and optimization","authors":"I. Khalil, H. Rueda, Damon Holmes, P. Chakraborty, D. Burdeaux","doi":"10.23919/EUMIC.2017.8230652","DOIUrl":"https://doi.org/10.23919/EUMIC.2017.8230652","url":null,"abstract":"A modeling method for RF power transistor fingers and large discrete die is presented in order to evaluate, visualize, and optimize various performance parameters at the device finger level. The model is constructed using a combination of TCAD based active die model and passive interconnect models based on Wheeler's transmission line formulation. Active die model of a fraction of the total periphery are connected with the interconnect models to build arbitrarily sized RF power transistors. The advantage of such model is shown to be flexibility of probing different parameters (e.g. voltage, current) at distinct die locations. Additionally, interconnect of the power transistor can be optimized in the simulation space in order to realize improved performance.","PeriodicalId":120932,"journal":{"name":"2017 12th European Microwave Integrated Circuits Conference (EuMIC)","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115606813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.23919/EUMIC.2017.8230658
Hebat-Allah Yehia Abdeen, S. Yuan, H. Schumacher, V. Ziegler, A. Meusling
This paper presents a 40–45 GHz high intermediate frequency (IF) stage for an extremely wide tuning range (10–40 GHz) receiver, in a 250 GHz fT SiGe BiCMOS process. The chip of the high IF stage down-converts the input 40–45 GHz signal to a low second IF of 0.2 to 4 GHz using a frequency multiplied tunable 10.875–11.875 GHz LO signal. The chip consists of a single-ended input/differential output amplifier, a fully balanced down-converting mixer driven by an on-chip LO quadrupler with single-ended input, and a fully differential variable gain amplifier. On-wafer characterization of the chip was performed. The IF stage achieves a differential conversion gain varying from 0 to 25.5 dB and an input-referred 1 dB compression point ranging from −9 to −17.5 dBm while varying the control voltage from 1.25 to 2.8 V. The chip with a highly symmetric layout occupies an area of 1.26 mm2. It consumes 670 mW.
{"title":"40–45 GHz high-IF stage for extremely wide tuning range receivers in 0.13 μm SiGe BiCMOS","authors":"Hebat-Allah Yehia Abdeen, S. Yuan, H. Schumacher, V. Ziegler, A. Meusling","doi":"10.23919/EUMIC.2017.8230658","DOIUrl":"https://doi.org/10.23919/EUMIC.2017.8230658","url":null,"abstract":"This paper presents a 40–45 GHz high intermediate frequency (IF) stage for an extremely wide tuning range (10–40 GHz) receiver, in a 250 GHz fT SiGe BiCMOS process. The chip of the high IF stage down-converts the input 40–45 GHz signal to a low second IF of 0.2 to 4 GHz using a frequency multiplied tunable 10.875–11.875 GHz LO signal. The chip consists of a single-ended input/differential output amplifier, a fully balanced down-converting mixer driven by an on-chip LO quadrupler with single-ended input, and a fully differential variable gain amplifier. On-wafer characterization of the chip was performed. The IF stage achieves a differential conversion gain varying from 0 to 25.5 dB and an input-referred 1 dB compression point ranging from −9 to −17.5 dBm while varying the control voltage from 1.25 to 2.8 V. The chip with a highly symmetric layout occupies an area of 1.26 mm2. It consumes 670 mW.","PeriodicalId":120932,"journal":{"name":"2017 12th European Microwave Integrated Circuits Conference (EuMIC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123491264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.23919/EUMIC.2017.8230682
R. Costanzo, Zhanyu Yang, Nicolas Raduazo, A. Beling, S. Bowers
A 10 GHz bandwidth photoreceiver is demonstrated. The photoreceiver consists of two photodiodes (PD) in a balanced configuration to generate a single-ended input to the transimpedance amplifier (TIA). The PDs achieves a responsivity of 0.48 A/W, and a 15 GHz bandwidth while driving a 50 D load under the designed biasing. The regulated cascode TIA is implemented in a 130 nm RF CMOS process. The TIA achieves a transimpedance gain of 39 dBD The complete photoreceiver achieves a conversion gain of 41 V/W across a 10 GHz bandwidth with the TIA consuming 56 mW from a 2 V supply, and the PDs drawing 1.2 mA from +/−5 V supplies. High sensitivity is achieved due to a low noise equivalent power (NEP) of 86 pWA/Hz.
{"title":"A 10 GHz bandwidth balanced photoreceiver with 41 V/W optical conversion gain","authors":"R. Costanzo, Zhanyu Yang, Nicolas Raduazo, A. Beling, S. Bowers","doi":"10.23919/EUMIC.2017.8230682","DOIUrl":"https://doi.org/10.23919/EUMIC.2017.8230682","url":null,"abstract":"A 10 GHz bandwidth photoreceiver is demonstrated. The photoreceiver consists of two photodiodes (PD) in a balanced configuration to generate a single-ended input to the transimpedance amplifier (TIA). The PDs achieves a responsivity of 0.48 A/W, and a 15 GHz bandwidth while driving a 50 D load under the designed biasing. The regulated cascode TIA is implemented in a 130 nm RF CMOS process. The TIA achieves a transimpedance gain of 39 dBD The complete photoreceiver achieves a conversion gain of 41 V/W across a 10 GHz bandwidth with the TIA consuming 56 mW from a 2 V supply, and the PDs drawing 1.2 mA from +/−5 V supplies. High sensitivity is achieved due to a low noise equivalent power (NEP) of 86 pWA/Hz.","PeriodicalId":120932,"journal":{"name":"2017 12th European Microwave Integrated Circuits Conference (EuMIC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124855714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.23919/EUMIC.2017.8230647
M. van Delden, N. Pohl, K. Aufinger, T. Musch
We present a fully programmable frequency divider in two different versions operating at input frequencies from DC to 94 GHz and 92 GHz, respectively, for the use in wideband and highly stable millimeter-wave frequency synthesizers. Using a parallel interface the division factors can be programmed to all integer values between 12 and 259. The high input speed in conjunction with programmability is achieved by a dual-modulus concept utilizing gates in emitter-coupled logic with inductive shunt peaking and by merging logic functions into flip-flops. The two versions utilize different differential spiral inductors. The frequency dividers were realized in a SiGe BiCMOS technology with fT = 250 GHz and are draining a current of 120 mA from a 3.3 V supply.
{"title":"A 94 GHz programmable frequency divider with inductive peaking for wideband and highly stable frequency synthesizers","authors":"M. van Delden, N. Pohl, K. Aufinger, T. Musch","doi":"10.23919/EUMIC.2017.8230647","DOIUrl":"https://doi.org/10.23919/EUMIC.2017.8230647","url":null,"abstract":"We present a fully programmable frequency divider in two different versions operating at input frequencies from DC to 94 GHz and 92 GHz, respectively, for the use in wideband and highly stable millimeter-wave frequency synthesizers. Using a parallel interface the division factors can be programmed to all integer values between 12 and 259. The high input speed in conjunction with programmability is achieved by a dual-modulus concept utilizing gates in emitter-coupled logic with inductive shunt peaking and by merging logic functions into flip-flops. The two versions utilize different differential spiral inductors. The frequency dividers were realized in a SiGe BiCMOS technology with fT = 250 GHz and are draining a current of 120 mA from a 3.3 V supply.","PeriodicalId":120932,"journal":{"name":"2017 12th European Microwave Integrated Circuits Conference (EuMIC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127686203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.23919/EUMIC.2017.8230689
M. Khafaji, Jan Plíva, M. Zoldak, R. Henker, F. Ellinger
In this paper the design and measurement results of a 42 Gbps vertical-cavity surface-emitting laser (VCSEL) driver is presented. A 2-tap feed-forward equalizer (FFE) architecture with adjustable delay is chosen and optimized to decrease the inter-symbol interference of the VCSEL data transmission. Circuit realizations of different blocks are presented as well. The chip was fabricated in a 14 nm SOI CMOS technology and bonded to a common-cathode 20 GHz VCSEL. Optical measurements show that error-free data transmission up to a data rate of 42 Gbps was possible. The total power dissipation, including the one of the VCSEL, is 117 mW, which provides a power efficiency of 2.8 pJ/bit. To the best of the author's knowledge, this is fastest VCSEL driver circuit in a CMOS technology presented so far.
本文介绍了42 Gbps垂直腔面发射激光器(VCSEL)驱动器的设计和测量结果。为了降低VCSEL数据传输中的码间干扰，选择并优化了具有可调延迟的2分路前馈均衡器(FFE)结构。并给出了不同模块的电路实现。该芯片采用14nm SOI CMOS技术制造，并与共阴极20ghz VCSEL键合。光学测量表明，无差错数据传输高达42 Gbps的数据速率是可能的。包括VCSEL在内的总功耗为117 mW，功率效率为2.8 pJ/bit。据作者所知，这是迄今为止CMOS技术中最快的VCSEL驱动电路。
{"title":"A 42 Gbps VCSEL driver with adjustable 2-tap feed-forward equalizer in 14 nm SOI CMOS","authors":"M. Khafaji, Jan Plíva, M. Zoldak, R. Henker, F. Ellinger","doi":"10.23919/EUMIC.2017.8230689","DOIUrl":"https://doi.org/10.23919/EUMIC.2017.8230689","url":null,"abstract":"In this paper the design and measurement results of a 42 Gbps vertical-cavity surface-emitting laser (VCSEL) driver is presented. A 2-tap feed-forward equalizer (FFE) architecture with adjustable delay is chosen and optimized to decrease the inter-symbol interference of the VCSEL data transmission. Circuit realizations of different blocks are presented as well. The chip was fabricated in a 14 nm SOI CMOS technology and bonded to a common-cathode 20 GHz VCSEL. Optical measurements show that error-free data transmission up to a data rate of 42 Gbps was possible. The total power dissipation, including the one of the VCSEL, is 117 mW, which provides a power efficiency of 2.8 pJ/bit. To the best of the author's knowledge, this is fastest VCSEL driver circuit in a CMOS technology presented so far.","PeriodicalId":120932,"journal":{"name":"2017 12th European Microwave Integrated Circuits Conference (EuMIC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128141255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.23919/EUMIC.2017.8230702
D. Maurath, A. Tavakoli, S. Vehring, P. Scholz, Yaoshun Ding, G. Boeck, F. Gerfers
This paper presents a power-efficient low-phase noise digitally controlled oscillator (DCO) implemented in a 65 nm CMOS technology. The DCO is designed for a 12 GHz frequency synthesizer covering up to 1GHz of frequency sweep range demanded by the frequency modulated continuous wave (FMCW) radar. The realized DCO circuit is designed to meet the stringent phase noise specifications of less than −110dBc/Hz @ 1MHz, required by the high resolution industrial indoor secondary FMCW radar system. The 12 GHz frequency synthesizer is based on a fractional-N all digital phased looked-loop (ADPLL) achieving a tuning range of 18.8 % using an 8-bit capacitive DAC array. This way, the DCO reliably covers up to 1GHz of frequency sweep range plus PVT variations. The low-power design achieves a phase noise performance of better than −112.3 dBc/Hz at a 1MHz offset. In summary, the DCO achieves a best in class figure of merit (FOMT) value of −186.7 dB with largest tuning range of 18.8 %, while only consuming 16.4 mW.
{"title":"A low-phase noise 12 GHz digitally controlled oscillator in 65 nm CMOS for a FMCW radar frequency synthesizer","authors":"D. Maurath, A. Tavakoli, S. Vehring, P. Scholz, Yaoshun Ding, G. Boeck, F. Gerfers","doi":"10.23919/EUMIC.2017.8230702","DOIUrl":"https://doi.org/10.23919/EUMIC.2017.8230702","url":null,"abstract":"This paper presents a power-efficient low-phase noise digitally controlled oscillator (DCO) implemented in a 65 nm CMOS technology. The DCO is designed for a 12 GHz frequency synthesizer covering up to 1GHz of frequency sweep range demanded by the frequency modulated continuous wave (FMCW) radar. The realized DCO circuit is designed to meet the stringent phase noise specifications of less than −110dBc/Hz @ 1MHz, required by the high resolution industrial indoor secondary FMCW radar system. The 12 GHz frequency synthesizer is based on a fractional-N all digital phased looked-loop (ADPLL) achieving a tuning range of 18.8 % using an 8-bit capacitive DAC array. This way, the DCO reliably covers up to 1GHz of frequency sweep range plus PVT variations. The low-power design achieves a phase noise performance of better than −112.3 dBc/Hz at a 1MHz offset. In summary, the DCO achieves a best in class figure of merit (FOMT) value of −186.7 dB with largest tuning range of 18.8 %, while only consuming 16.4 mW.","PeriodicalId":120932,"journal":{"name":"2017 12th European Microwave Integrated Circuits Conference (EuMIC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134584885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.23919/EUMIC.2017.8230683
A. Bauch, M. Dietz, R. Weigel, A. Hagelauer, D. Kissinger
A wideband variable gain amplifier in a 130 nm BiCMOS technology has been designed, manufactured and characterized. The VGA is built of two cascaded differential emitter follower stages, followed by a cascode stage implemented by a common emitter stage and a common base stage. The combination of emitter follower stages with the cascode stage allows a considerably wider frequency response from DC to 110 GHz. It has been shown that a high-pass response can be achieved using emitter follower stages. The high-pass response is cascaded with the low-pass response of the cascode stage to realize a flat broadband output characteristic. This design method requires significantly less chip area than conventional used distributed amplifier for this bandwidth. The area needed for this VGA is 0.024 mm2. The amplifier consumes a current of 80 mA at a supply voltage of 3.3 V.
{"title":"A broadband 10–95 GHz variable gain amplifier in a 130 nm BiCMOS technology","authors":"A. Bauch, M. Dietz, R. Weigel, A. Hagelauer, D. Kissinger","doi":"10.23919/EUMIC.2017.8230683","DOIUrl":"https://doi.org/10.23919/EUMIC.2017.8230683","url":null,"abstract":"A wideband variable gain amplifier in a 130 nm BiCMOS technology has been designed, manufactured and characterized. The VGA is built of two cascaded differential emitter follower stages, followed by a cascode stage implemented by a common emitter stage and a common base stage. The combination of emitter follower stages with the cascode stage allows a considerably wider frequency response from DC to 110 GHz. It has been shown that a high-pass response can be achieved using emitter follower stages. The high-pass response is cascaded with the low-pass response of the cascode stage to realize a flat broadband output characteristic. This design method requires significantly less chip area than conventional used distributed amplifier for this bandwidth. The area needed for this VGA is 0.024 mm2. The amplifier consumes a current of 80 mA at a supply voltage of 3.3 V.","PeriodicalId":120932,"journal":{"name":"2017 12th European Microwave Integrated Circuits Conference (EuMIC)","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114998349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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