Pub Date : 2017-10-01DOI: 10.23919/EUMIC.2017.8230668
G. C. Barisich, E. Gebara, Huifang Gu, C. Storey, Pouya Aflaki, J. Papapolymerou
A 3-stage wideband power amplifier (PA) using a 0.15 pm gallium nitride (GaN) monolithic microwave integrated circuit (MMIC) process from NRC is designed, fabricated, and measured. After characterization of the high electron mobility transistor (HEMT), a non-linear model was created from the measured data for use in the design. The reactively matched 3.8 mm × 1.8 mm PA also uses resistive elements for gain compensation and circuit stability. Measurements at 20 dBm source power show 35–38 dBm output power and 10–18% PAE over a 6 to 17 GHz bandwidth. These results demonstrate the highest output power per die area for a 3-stage GaN MMIC PA of this bandwidth in this power range.
采用NRC的0.15 pm氮化镓(GaN)单片微波集成电路(MMIC)工艺设计、制作和测量了一种三级宽带功率放大器(PA)。在对高电子迁移率晶体管(HEMT)进行表征后，根据测量数据创建了一个非线性模型，用于设计。响应匹配的3.8 mm × 1.8 mm PA还使用电阻元件进行增益补偿和电路稳定性。在20 dBm源功率下的测量显示，在6至17 GHz带宽上，输出功率为35-38 dBm, PAE为10-18%。这些结果表明，在此功率范围内，此带宽的3级GaN MMIC PA的每个芯片面积的最高输出功率。
{"title":"Reactively matched 3-stage C-X-Ku band GaN MMIC power amplifier","authors":"G. C. Barisich, E. Gebara, Huifang Gu, C. Storey, Pouya Aflaki, J. Papapolymerou","doi":"10.23919/EUMIC.2017.8230668","DOIUrl":"https://doi.org/10.23919/EUMIC.2017.8230668","url":null,"abstract":"A 3-stage wideband power amplifier (PA) using a 0.15 pm gallium nitride (GaN) monolithic microwave integrated circuit (MMIC) process from NRC is designed, fabricated, and measured. After characterization of the high electron mobility transistor (HEMT), a non-linear model was created from the measured data for use in the design. The reactively matched 3.8 mm × 1.8 mm PA also uses resistive elements for gain compensation and circuit stability. Measurements at 20 dBm source power show 35–38 dBm output power and 10–18% PAE over a 6 to 17 GHz bandwidth. These results demonstrate the highest output power per die area for a 3-stage GaN MMIC PA of this bandwidth in this power range.","PeriodicalId":120932,"journal":{"name":"2017 12th European Microwave Integrated Circuits Conference (EuMIC)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128864799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.23919/EUMIC.2017.8230720
Siqi Wang, M. A. Hussein, O. Venard, G. Baudoin
This paper studies the impact of gain scaling on linearization performance and power added efficiency (PAE) of a power amplifier (PA) using digital predistortion (DPD). The performance of the DPD designed at different operating points of PA with different choices of gain are compared. An adjustment in iterative DPD identification procedure is proposed to improve the convergence. The performances are evaluated experimentally with a 500-W peak Three-way Doherty PA.
{"title":"Impact of the normalization gain of digital predistortion on linearization performance and power added efficiency of the linearized power amplifier","authors":"Siqi Wang, M. A. Hussein, O. Venard, G. Baudoin","doi":"10.23919/EUMIC.2017.8230720","DOIUrl":"https://doi.org/10.23919/EUMIC.2017.8230720","url":null,"abstract":"This paper studies the impact of gain scaling on linearization performance and power added efficiency (PAE) of a power amplifier (PA) using digital predistortion (DPD). The performance of the DPD designed at different operating points of PA with different choices of gain are compared. An adjustment in iterative DPD identification procedure is proposed to improve the convergence. The performances are evaluated experimentally with a 500-W peak Three-way Doherty PA.","PeriodicalId":120932,"journal":{"name":"2017 12th European Microwave Integrated Circuits Conference (EuMIC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124098918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.23919/EUMIC.2017.8230662
Himanshu Aggrawal, A. Babakhani
In this paper, a novel nonlinear impulse sampler is presented. The architecture uses an ultrafast transmissionline based inductive peaking technique to turn on a high-speed sampling bipolar transistor for a few picoseconds. It is shown that the sampler can detect impulses as short as 100 ps. The chip is fabricated in IBM 9HP BiCMOS process technology and occupies an area of 1.02 mm2. The power consumption of the chip is 105 mW.
{"title":"A nonlinear impulse sampler for detection of picosecond pulses in 90 nm SiGe BiCMOS","authors":"Himanshu Aggrawal, A. Babakhani","doi":"10.23919/EUMIC.2017.8230662","DOIUrl":"https://doi.org/10.23919/EUMIC.2017.8230662","url":null,"abstract":"In this paper, a novel nonlinear impulse sampler is presented. The architecture uses an ultrafast transmissionline based inductive peaking technique to turn on a high-speed sampling bipolar transistor for a few picoseconds. It is shown that the sampler can detect impulses as short as 100 ps. The chip is fabricated in IBM 9HP BiCMOS process technology and occupies an area of 1.02 mm2. The power consumption of the chip is 105 mW.","PeriodicalId":120932,"journal":{"name":"2017 12th European Microwave Integrated Circuits Conference (EuMIC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133341241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.23919/EUMIC.2017.8230695
G. P. Gibiino, R. Cignani, A. Santarelli, F. Filicori
An empirical Gallium Nitride (GaN) HEMT model, suitable for multi-bias and multi-class power amplifier (PA) performance prediction, is formulated. In addition to the fast dynamically-nonlinear capture mechanisms normally considered for local modeling, dynamically-linear charge trapping is taken into account here. A straightforward empirical identification procedure based on tailored double-pulsed IV measurements is described. Validation experiments carried out on a 8×125 pm (gate length: 0.25 pm) GaN-on-SiC HEMT show good model prediction capabilities under different drain bias conditions and class AB, B, and C large-signal PA operation at both low-frequency (f = 4 MHz) and RF (f = 2.5 GHz).
{"title":"Global modeling of GaN HEMT resistive current including charge trapping and self-heating for multi-bias multi-class PA performance prediction","authors":"G. P. Gibiino, R. Cignani, A. Santarelli, F. Filicori","doi":"10.23919/EUMIC.2017.8230695","DOIUrl":"https://doi.org/10.23919/EUMIC.2017.8230695","url":null,"abstract":"An empirical Gallium Nitride (GaN) HEMT model, suitable for multi-bias and multi-class power amplifier (PA) performance prediction, is formulated. In addition to the fast dynamically-nonlinear capture mechanisms normally considered for local modeling, dynamically-linear charge trapping is taken into account here. A straightforward empirical identification procedure based on tailored double-pulsed IV measurements is described. Validation experiments carried out on a 8×125 pm (gate length: 0.25 pm) GaN-on-SiC HEMT show good model prediction capabilities under different drain bias conditions and class AB, B, and C large-signal PA operation at both low-frequency (f = 4 MHz) and RF (f = 2.5 GHz).","PeriodicalId":120932,"journal":{"name":"2017 12th European Microwave Integrated Circuits Conference (EuMIC)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131773772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.23919/EUMIC.2017.8230686
Arash Ebrahimi Jarihani, F. Koçer
We present a novel digital step attenuator (DSA) with low phase variation under attenuation state and frequency changes. This is achieved while keeping all other specifications comparable with the state-of-the-art. To compensate the phase shift, a number of switchable phase compensating blocks are employed. Unlike previous studies, this work achieves very low phase variation in a commercial, 4×4 quad-flat no-leads (QFN) package, where wirebond effects are significant. The proposed attenuator has 7-bit control with 0 to 31.75 dB attenuation range with 0.25 dB step sizes and achieves accurate attenuation settings in a wide frequency range. The attenuator is fabricated in a commercial 0.18 pm RF silicon-on-insulator (SOI) process. The measurement results show that the attenuator has an amplitude error of less than 1 dB, while introducing a maximum of ±3° phase shift up to 2.2 GHz and less than ±6° between 2.2–3.5 GHz. This approach provides at least 2.5-fold improvement in the phase shift when compared to commercial attenuators. The input 1 dB compression point and IIP3 are measured typically higher than 35 dBm and 45 dBm, respectively. Total chip size, including pads, is 1.95mm × 0.95mm.
{"title":"A phase coherent 7-bit digital step attenuator on 0.18μm SOI","authors":"Arash Ebrahimi Jarihani, F. Koçer","doi":"10.23919/EUMIC.2017.8230686","DOIUrl":"https://doi.org/10.23919/EUMIC.2017.8230686","url":null,"abstract":"We present a novel digital step attenuator (DSA) with low phase variation under attenuation state and frequency changes. This is achieved while keeping all other specifications comparable with the state-of-the-art. To compensate the phase shift, a number of switchable phase compensating blocks are employed. Unlike previous studies, this work achieves very low phase variation in a commercial, 4×4 quad-flat no-leads (QFN) package, where wirebond effects are significant. The proposed attenuator has 7-bit control with 0 to 31.75 dB attenuation range with 0.25 dB step sizes and achieves accurate attenuation settings in a wide frequency range. The attenuator is fabricated in a commercial 0.18 pm RF silicon-on-insulator (SOI) process. The measurement results show that the attenuator has an amplitude error of less than 1 dB, while introducing a maximum of ±3° phase shift up to 2.2 GHz and less than ±6° between 2.2–3.5 GHz. This approach provides at least 2.5-fold improvement in the phase shift when compared to commercial attenuators. The input 1 dB compression point and IIP3 are measured typically higher than 35 dBm and 45 dBm, respectively. Total chip size, including pads, is 1.95mm × 0.95mm.","PeriodicalId":120932,"journal":{"name":"2017 12th European Microwave Integrated Circuits Conference (EuMIC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133912542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.23919/EUMIC.2017.8230707
T. Martín-Guerrero, J. T. Entrambasaguas, C. Camacho-Peñalosa
A charge-controlled, one-port device is used to describe and discuss the extraction procedure of a Poly-Harmonic Distortion (PHD) model in detail. For this case, both voltage and current waveforms are shown to be enough to fully characterize the PHD model. It is also shown that all the information specifically required for this PHD model definition can be stored in the Fourier coefficients of the incremental conductance and capacitance. The results are validated by comparing them with those obtained using a commercial circuit simulation tool.
{"title":"Poly-harmonic distortion model extraction in charge-controlled one-port devices","authors":"T. Martín-Guerrero, J. T. Entrambasaguas, C. Camacho-Peñalosa","doi":"10.23919/EUMIC.2017.8230707","DOIUrl":"https://doi.org/10.23919/EUMIC.2017.8230707","url":null,"abstract":"A charge-controlled, one-port device is used to describe and discuss the extraction procedure of a Poly-Harmonic Distortion (PHD) model in detail. For this case, both voltage and current waveforms are shown to be enough to fully characterize the PHD model. It is also shown that all the information specifically required for this PHD model definition can be stored in the Fourier coefficients of the incremental conductance and capacitance. The results are validated by comparing them with those obtained using a commercial circuit simulation tool.","PeriodicalId":120932,"journal":{"name":"2017 12th European Microwave Integrated Circuits Conference (EuMIC)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130277173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.23919/EUMIC.2017.8230717
X. Hue, Faiza Baroudi, L. Bollinger, M. Szymanowski, Jean-Christophe Nanan
This paper presents the design of a wideband 2 stage Power Amplifier IC using the latest LDMOS Technology. This IC, easily adaptable for 12W & 25W applications, can be used as a driver or as a Doherty PA. For driver applications, the Proof of Concept demonstrates very flat performances over 3200–4000 MHz with high Gain, good Linearity and high Efficiency performances in class AB. Linear Gain is better than 27 dB with P3dB=42.8 dBm and 45.5 dBm respectively for both versions. Drain Efficiency remains better than 54% at P3dB. In Doherty configuration, those ICs have confirmed their ability to be used with complex LTE signals. With symmetric ICs, good linearity performances can be achieved even when the part is driven with up to 200MHz wideband LTE signal. The asymmetric POC delivered a P3dB of 44.5 dBm over the 3400–3600 MHz band with at least 25 dB linear Gain. Driven with 3 carrier LTE signal (60MHz), drain Efficiency is better than 40% at 8dB OBO. With respect to the state of the art, to the best of our knowledge, it is the highest performance LDMOS PA IC which meets 5G requirements in 3.4–3.8GHz band. Those ICs demonstrated their applicability for 5G applications in the 3.4–3.8GHz band.
{"title":"12/25W wideband LDMOS Power Amplifier IC (3400–3800MHz) For 5G base station applications","authors":"X. Hue, Faiza Baroudi, L. Bollinger, M. Szymanowski, Jean-Christophe Nanan","doi":"10.23919/EUMIC.2017.8230717","DOIUrl":"https://doi.org/10.23919/EUMIC.2017.8230717","url":null,"abstract":"This paper presents the design of a wideband 2 stage Power Amplifier IC using the latest LDMOS Technology. This IC, easily adaptable for 12W & 25W applications, can be used as a driver or as a Doherty PA. For driver applications, the Proof of Concept demonstrates very flat performances over 3200–4000 MHz with high Gain, good Linearity and high Efficiency performances in class AB. Linear Gain is better than 27 dB with P3dB=42.8 dBm and 45.5 dBm respectively for both versions. Drain Efficiency remains better than 54% at P3dB. In Doherty configuration, those ICs have confirmed their ability to be used with complex LTE signals. With symmetric ICs, good linearity performances can be achieved even when the part is driven with up to 200MHz wideband LTE signal. The asymmetric POC delivered a P3dB of 44.5 dBm over the 3400–3600 MHz band with at least 25 dB linear Gain. Driven with 3 carrier LTE signal (60MHz), drain Efficiency is better than 40% at 8dB OBO. With respect to the state of the art, to the best of our knowledge, it is the highest performance LDMOS PA IC which meets 5G requirements in 3.4–3.8GHz band. Those ICs demonstrated their applicability for 5G applications in the 3.4–3.8GHz band.","PeriodicalId":120932,"journal":{"name":"2017 12th European Microwave Integrated Circuits Conference (EuMIC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114268548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.23919/EUMIC.2017.8230677
A. Leuther, M. Ohlrogge, L. Czornomaz, T. Merkle, F. Bernhardt, A. Tessmann
A 30 nm gate length InGaAs channel MOSFET MMIC technology is presented. 100 mm semi-insulating GaAs substrates with a metamorphicaly grown InGaAs/InAlAs device heterostructure are used. Al2O3 is deposited as gate dielectric onto the In08Ga02As channel by atomic layer deposition. The gate layout was optimized for monolithic microwave integrated circuit (MMIC) applications using T-gates and wet chemical recess etching to minimize the parasitic gate capacitances. For a 2 × 20 μm gate width transistor a transit frequency fT of 306 GHz and a maximum oscillation frequency fmax of 381 GHz was extrapolated, respectively. This technology was employed for the fabrication of a 230–275 GHz amplifier MMIC with 4 cascode stages achieving a small signal gain of 12 dB at 250 GHz. To the best of the authors knowledge, this is the first reported InGaAs MOSFET millimeter-wave amplifier MMIC operated in the frequency regime beyond W-band.
{"title":"A 250 GHz millimeter wave amplifier MMIC based on 30 nm metamorphic InGaAs MOSFET technology","authors":"A. Leuther, M. Ohlrogge, L. Czornomaz, T. Merkle, F. Bernhardt, A. Tessmann","doi":"10.23919/EUMIC.2017.8230677","DOIUrl":"https://doi.org/10.23919/EUMIC.2017.8230677","url":null,"abstract":"A 30 nm gate length InGaAs channel MOSFET MMIC technology is presented. 100 mm semi-insulating GaAs substrates with a metamorphicaly grown InGaAs/InAlAs device heterostructure are used. Al2O3 is deposited as gate dielectric onto the In08Ga02As channel by atomic layer deposition. The gate layout was optimized for monolithic microwave integrated circuit (MMIC) applications using T-gates and wet chemical recess etching to minimize the parasitic gate capacitances. For a 2 × 20 μm gate width transistor a transit frequency fT of 306 GHz and a maximum oscillation frequency fmax of 381 GHz was extrapolated, respectively. This technology was employed for the fabrication of a 230–275 GHz amplifier MMIC with 4 cascode stages achieving a small signal gain of 12 dB at 250 GHz. To the best of the authors knowledge, this is the first reported InGaAs MOSFET millimeter-wave amplifier MMIC operated in the frequency regime beyond W-band.","PeriodicalId":120932,"journal":{"name":"2017 12th European Microwave Integrated Circuits Conference (EuMIC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117227102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.23919/EUMIC.2017.8230747
K. Hamano, R. Tanaka, S. Yoshida, H. Sakaki, K. Nishikawa, S. Kawasaki, K. Kawai, H. Okazaki, S. Narahashi, N. Shinohara
This paper proposes and demonstrates a novel wide dynamic range rectifier. The proposed rectifier consists of two rectifying circuits in parallel, an asymmetrical output impedance power divider for RF input signal, and a DC combiner. The asymmetric power divider sequentially distributes the RF signal to the rectifier for high input power from the rectifier for low input power without switch devices, according as the input signal power level increases. The fabricated 2.45 GHz rectifier verified the proposed technique and expanded the operating input power range. The fabricated rectifier demonstrated more than 25dB dynamic range with an efficiency of higher than 30%. The maximum efficiency of the rectifier achieved 47.5% at 15dBm input power.
{"title":"Wide dynamic range rectifier circuit with sequential power delivery technique","authors":"K. Hamano, R. Tanaka, S. Yoshida, H. Sakaki, K. Nishikawa, S. Kawasaki, K. Kawai, H. Okazaki, S. Narahashi, N. Shinohara","doi":"10.23919/EUMIC.2017.8230747","DOIUrl":"https://doi.org/10.23919/EUMIC.2017.8230747","url":null,"abstract":"This paper proposes and demonstrates a novel wide dynamic range rectifier. The proposed rectifier consists of two rectifying circuits in parallel, an asymmetrical output impedance power divider for RF input signal, and a DC combiner. The asymmetric power divider sequentially distributes the RF signal to the rectifier for high input power from the rectifier for low input power without switch devices, according as the input signal power level increases. The fabricated 2.45 GHz rectifier verified the proposed technique and expanded the operating input power range. The fabricated rectifier demonstrated more than 25dB dynamic range with an efficiency of higher than 30%. The maximum efficiency of the rectifier achieved 47.5% at 15dBm input power.","PeriodicalId":120932,"journal":{"name":"2017 12th European Microwave Integrated Circuits Conference (EuMIC)","volume":"146 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116515148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.23919/EUMIC.2017.8230742
Carlos Mateo, P. L. Carro, Paloma García-Dúcar, J. de Mingo, Iñigo Salinas
A novel modeling and linearization model for a Radio over Fiber (RoF) LTE mobile fronthaul system is proposed in order to reduce the canonical piece-wise-linear (CPWL) model order without compromising its performance. The proposed basis is composed by cubic spline functions (B-splines basis), whose features guarantee the proposed model (BS-CPWL) accuracy when the model order is low. A 10MHz-LTE downlink signal (16QAM) is applied in order to carry out the measurements. We have experimentally demonstrated that the proposed model improves not only the modeling of the intensity modulation/direct detection (IM/DD) RoF system but also the distortion reduction, as the adjacent channel power ratio (ACPR) and error vector magnitude (EVM) values show, fulfilling the standard requirements.
{"title":"Digital predistortion based on B-spline CPWL models in a RoF LTE mobile fronthaul","authors":"Carlos Mateo, P. L. Carro, Paloma García-Dúcar, J. de Mingo, Iñigo Salinas","doi":"10.23919/EUMIC.2017.8230742","DOIUrl":"https://doi.org/10.23919/EUMIC.2017.8230742","url":null,"abstract":"A novel modeling and linearization model for a Radio over Fiber (RoF) LTE mobile fronthaul system is proposed in order to reduce the canonical piece-wise-linear (CPWL) model order without compromising its performance. The proposed basis is composed by cubic spline functions (B-splines basis), whose features guarantee the proposed model (BS-CPWL) accuracy when the model order is low. A 10MHz-LTE downlink signal (16QAM) is applied in order to carry out the measurements. We have experimentally demonstrated that the proposed model improves not only the modeling of the intensity modulation/direct detection (IM/DD) RoF system but also the distortion reduction, as the adjacent channel power ratio (ACPR) and error vector magnitude (EVM) values show, fulfilling the standard requirements.","PeriodicalId":120932,"journal":{"name":"2017 12th European Microwave Integrated Circuits Conference (EuMIC)","volume":"696 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122981155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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