K. Soejima, A. Shida, M. Hirata, H. Koga, J. Ukai, H. Sata
A BiCMOS technology with a triple-diffused vertical p-n-p transistor has been developed to meet wide-bandwidth requirements for mixed analog/digital application-specific integrated circuits (ASICs). An fT of 660 MHz and BVceo of over 15 V were obtained for the p-n-p transistor, by adding only one extra mask to a conventional 2.0-μm BiCMOS process (a total of 20 masks for double-layer metallization). A unity-gain frequency of 52 MHz and DC gain of over 85 dB were obtained for a single-supply operational amplifier with p-n-p first stage. A propagation delay time of 1.27 ns for a CMOS 2 NAND gate has been obtained under a 3 F/O and 3-mm-length wiring load condition
{"title":"A BiCMOS technology with 660 MHz vertical PNP transistors for analog/digital ASICs","authors":"K. Soejima, A. Shida, M. Hirata, H. Koga, J. Ukai, H. Sata","doi":"10.1109/CICC.1989.56785","DOIUrl":"https://doi.org/10.1109/CICC.1989.56785","url":null,"abstract":"A BiCMOS technology with a triple-diffused vertical p-n-p transistor has been developed to meet wide-bandwidth requirements for mixed analog/digital application-specific integrated circuits (ASICs). An fT of 660 MHz and BVceo of over 15 V were obtained for the p-n-p transistor, by adding only one extra mask to a conventional 2.0-μm BiCMOS process (a total of 20 masks for double-layer metallization). A unity-gain frequency of 52 MHz and DC gain of over 85 dB were obtained for a single-supply operational amplifier with p-n-p first stage. A propagation delay time of 1.27 ns for a CMOS 2 NAND gate has been obtained under a 3 F/O and 3-mm-length wiring load condition","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122021081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A description is given of the design and integrated-circuit implementation of a fifth-order elliptic lowpass switched-capacitor (SC) video decimator with a cutoff frequency of 3.6 MHz and sampling rate reduction from 40.5 MHz to 13.5 MHz. A recently proposed decimator architecture used to make the settling time requirements of the operational amplifiers similar to those of a conventional SC filter with switching frequency of only 13.5 MHz. The circuit is implemented using a 2.4-μm CMOS double-poly process yielding a total area of less than 1 mm2. The power consumption is less than 50 mW with a 10-V power supply
{"title":"A 2.4 μm CMOS switched-capacitor video decimator with sampling rate reduction from 40.5 MHz to 13.5 MHz","authors":"R. Martins, J. Franca","doi":"10.1109/CICC.1989.56831","DOIUrl":"https://doi.org/10.1109/CICC.1989.56831","url":null,"abstract":"A description is given of the design and integrated-circuit implementation of a fifth-order elliptic lowpass switched-capacitor (SC) video decimator with a cutoff frequency of 3.6 MHz and sampling rate reduction from 40.5 MHz to 13.5 MHz. A recently proposed decimator architecture used to make the settling time requirements of the operational amplifiers similar to those of a conventional SC filter with switching frequency of only 13.5 MHz. The circuit is implemented using a 2.4-μm CMOS double-poly process yielding a total area of less than 1 mm2. The power consumption is less than 50 mW with a 10-V power supply","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"383 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126731683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A parameterizable generator that can generate macrocells with multilevel hierarchies is described. High-density macrocells that incorporate random logic can be laid out automatically. The system generates full-custom macrocell layouts, sea-of-gates masterslice layouts, standard cell descriptions for such macrocells, and equivalent logic and function models for chip-level simulations
{"title":"A generator for high-density macrocells with hierarchical structure","authors":"K. Takeya, M. Nagatani, S. Horiguchi","doi":"10.1109/CICC.1989.56818","DOIUrl":"https://doi.org/10.1109/CICC.1989.56818","url":null,"abstract":"A parameterizable generator that can generate macrocells with multilevel hierarchies is described. High-density macrocells that incorporate random logic can be laid out automatically. The system generates full-custom macrocell layouts, sea-of-gates masterslice layouts, standard cell descriptions for such macrocells, and equivalent logic and function models for chip-level simulations","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"349 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124303208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A closed-form analytic model for the transient response of a BiCMOS inverter has been demonstrated which allows the gate delay to be predicted with good accuracy over a wide range of circuit and device parameter values. In addition, the model has been shown to be accurate not only when the bipolar transistors operate in low-level injection, but in high-level injection and saturation as well. Since this is a closed-form model, it allows the user to examine the equations directly to determine how the gate delay depends on circuit and device parameters. Possible applications being pursued at this time by the authors include investigating BiCMOS logic performance at low temperatures as well as examining the consequences of physically separating the bipolar and CMOS components of the BiCMOS driver. This could occur in a hybrid packaging scheme which has CMOS chips placed on active silicon substrates in which the bipolar drivers are fabricated
{"title":"An analytical model for BiCMOS logic transient response allowing parameter variations","authors":"P. Heedley, R. Jaeger","doi":"10.1109/CICC.1989.56748","DOIUrl":"https://doi.org/10.1109/CICC.1989.56748","url":null,"abstract":"A closed-form analytic model for the transient response of a BiCMOS inverter has been demonstrated which allows the gate delay to be predicted with good accuracy over a wide range of circuit and device parameter values. In addition, the model has been shown to be accurate not only when the bipolar transistors operate in low-level injection, but in high-level injection and saturation as well. Since this is a closed-form model, it allows the user to examine the equations directly to determine how the gate delay depends on circuit and device parameters. Possible applications being pursued at this time by the authors include investigating BiCMOS logic performance at low temperatures as well as examining the consequences of physically separating the bipolar and CMOS components of the BiCMOS driver. This could occur in a hybrid packaging scheme which has CMOS chips placed on active silicon substrates in which the bipolar drivers are fabricated","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129831723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A 100-MHz, 1.5-μm CMOS point processor/demultiplexer and time base integrated circuit has been developed for use in a digitizing oscilloscope. The component uses a single +5-V supply, accepts standard, negative ECL (emitter-coupled logic)-level inputs, and contains 46000 devices on a 311-mil×325-mil die. Those aspects of the design that comprise novel or improved circuitry or design techniques are described
{"title":"A CMOS 100 MHz digital oscilloscope point processor and time base integrated circuit","authors":"E. Etheridge","doi":"10.1109/CICC.1989.56737","DOIUrl":"https://doi.org/10.1109/CICC.1989.56737","url":null,"abstract":"A 100-MHz, 1.5-μm CMOS point processor/demultiplexer and time base integrated circuit has been developed for use in a digitizing oscilloscope. The component uses a single +5-V supply, accepts standard, negative ECL (emitter-coupled logic)-level inputs, and contains 46000 devices on a 311-mil×325-mil die. Those aspects of the design that comprise novel or improved circuitry or design techniques are described","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131167129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Gill, R. Cleavelin, S. Lin, I. D'Arrigo, G. Santin, P. Shah, A. Nguyen, R. Lahiry, P. Desimone, G. Piva, J. Paterson
A CMOS contactless cell array technology has been developed for a single-power-supply high-density, five-V-only flash memory and for system programmable IC applications. The technology's suitability for VLSI memories has been demonstrated by a 256-kb flash EEPROM (electronically erasable programmable read-only memory) chip. This low-current five-V-only approach has been proved, with cell area and cost comparable to recently reported high-current dual-power-supply flash EEPROMs
{"title":"A five-volt only flash EEPROM technology for high density memory and system IC applications","authors":"M. Gill, R. Cleavelin, S. Lin, I. D'Arrigo, G. Santin, P. Shah, A. Nguyen, R. Lahiry, P. Desimone, G. Piva, J. Paterson","doi":"10.1109/CICC.1989.56783","DOIUrl":"https://doi.org/10.1109/CICC.1989.56783","url":null,"abstract":"A CMOS contactless cell array technology has been developed for a single-power-supply high-density, five-V-only flash memory and for system programmable IC applications. The technology's suitability for VLSI memories has been demonstrated by a 256-kb flash EEPROM (electronically erasable programmable read-only memory) chip. This low-current five-V-only approach has been proved, with cell area and cost comparable to recently reported high-current dual-power-supply flash EEPROMs","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132919591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Hara, Yasuhiro Sugimoto, M. Noda, T. Nagamatsu, Y. Watanabe, Hiroshi Iwai, Y. Niitsu, G. Sasaki, K. Maeguchi
A BiCMOS gate array with gate delay of 350 ps has been realized by 0.8-μm BiCMOS technology. Minimum gate delay and cell area have been achieved with a shared bipolar cell structure. The gate delay is almost equivalent to that of a 0.5-μm pure CMOS gate array. The cell-area increase is to only 25% compared with a 0.8-μm pure CMOS cell. I/O cells can interface with CMOS, TTL (transistor-transistor logic), and ECL (emitter-coupled logic) chips at the same time with a single supply voltage of 5 V
{"title":"A 350 ps 50 K 0.8 μm BiCMOS gate array with shared bipolar cell structure","authors":"H. Hara, Yasuhiro Sugimoto, M. Noda, T. Nagamatsu, Y. Watanabe, Hiroshi Iwai, Y. Niitsu, G. Sasaki, K. Maeguchi","doi":"10.1109/CICC.1989.56712","DOIUrl":"https://doi.org/10.1109/CICC.1989.56712","url":null,"abstract":"A BiCMOS gate array with gate delay of 350 ps has been realized by 0.8-μm BiCMOS technology. Minimum gate delay and cell area have been achieved with a shared bipolar cell structure. The gate delay is almost equivalent to that of a 0.5-μm pure CMOS gate array. The cell-area increase is to only 25% compared with a 0.8-μm pure CMOS cell. I/O cells can interface with CMOS, TTL (transistor-transistor logic), and ECL (emitter-coupled logic) chips at the same time with a single supply voltage of 5 V","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132143294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Takehisa Hayashi, T. Doi, M. Asai, K. Ishibashi, S. Shukuri, A. Watanabe, M. Suzuki
The shielded dynamic complex-gate (SDC) cell is a novel CMOS/BiCMOS cell-based design methodology for generating high-speed modules or macro-cells using precharged circuit technology. Since precharged circuits have inherent difficulties such as noise and clock distribution, cell-based design approaches using DA systems cannot be adopted. The SDC cell has been developed to solve this problem and requires as little design time as the poly-cell approach. The SDC cell has the following features: (1) noise-tolerant CMOS/BiCMOS precharged circuits; (2) a unique cell layout concept with a shielded structure; and (3) a clock distribution system design to minimize clock skew. Applications to a 32-bit ALU (arithmetic logic unit) and a mainframe execution unit (parallel adder) are also described
{"title":"SDC cell-a novel CMOS/BiCMOS design methodology for mainframe arithmetic module generation","authors":"Takehisa Hayashi, T. Doi, M. Asai, K. Ishibashi, S. Shukuri, A. Watanabe, M. Suzuki","doi":"10.1109/CICC.1989.56779","DOIUrl":"https://doi.org/10.1109/CICC.1989.56779","url":null,"abstract":"The shielded dynamic complex-gate (SDC) cell is a novel CMOS/BiCMOS cell-based design methodology for generating high-speed modules or macro-cells using precharged circuit technology. Since precharged circuits have inherent difficulties such as noise and clock distribution, cell-based design approaches using DA systems cannot be adopted. The SDC cell has been developed to solve this problem and requires as little design time as the poly-cell approach. The SDC cell has the following features: (1) noise-tolerant CMOS/BiCMOS precharged circuits; (2) a unique cell layout concept with a shielded structure; and (3) a clock distribution system design to minimize clock skew. Applications to a 32-bit ALU (arithmetic logic unit) and a mainframe execution unit (parallel adder) are also described","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133448706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A description is given of a computationally efficient SPICE model for accurate prediction of the I-V and threshold voltage characteristics of small-geometry MOSFETs. The model based on an enhancement of the SPICE LEVEL3 MOS model and a novel approach of parameter extraction. The expressions achieved for the drain currents hold in the weak inversion, strong inversion, and saturation regimes of operation. The model supports the design of both short-channel and narrow-gate MOSFETs with any kind of implanted channel. Accuracy and benchmark tests show substantial improvements over the original LEVEL3 model
{"title":"An improved I-V model of small geometry MOSFETs for SPICE","authors":"S. Chung, T. S. Lin, Yi-Ting Chen","doi":"10.1109/CICC.1989.56723","DOIUrl":"https://doi.org/10.1109/CICC.1989.56723","url":null,"abstract":"A description is given of a computationally efficient SPICE model for accurate prediction of the I-V and threshold voltage characteristics of small-geometry MOSFETs. The model based on an enhancement of the SPICE LEVEL3 MOS model and a novel approach of parameter extraction. The expressions achieved for the drain currents hold in the weak inversion, strong inversion, and saturation regimes of operation. The model supports the design of both short-channel and narrow-gate MOSFETs with any kind of implanted channel. Accuracy and benchmark tests show substantial improvements over the original LEVEL3 model","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"190 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132903824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A description is given of a hot-electron-effect analyzer incorporated into a critical path analysis tool, Ltime, for CMOS circuits. Using some empirical relationships, the author correlates the accumulated charge in the oxide to the size and capacitive load of the individual transistors. Effective stress time is calculated, using the time spent in the saturation region of each transistor, the results of a static switching probability analyzer, and the clock period. The methods developed can be used to predict circuit performance variation due to hot carriers as a function of time
{"title":"Hot carrier effects on CMOS circuit performance","authors":"M. Cirit","doi":"10.1109/CICC.1989.56839","DOIUrl":"https://doi.org/10.1109/CICC.1989.56839","url":null,"abstract":"A description is given of a hot-electron-effect analyzer incorporated into a critical path analysis tool, Ltime, for CMOS circuits. Using some empirical relationships, the author correlates the accumulated charge in the oxide to the size and capacitive load of the individual transistors. Effective stress time is calculated, using the time spent in the saturation region of each transistor, the results of a static switching probability analyzer, and the clock period. The methods developed can be used to predict circuit performance variation due to hot carriers as a function of time","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114040655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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