Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791779
Christian Maleck, Gottfried Nieke, K. Bock, Detlef Pabst, M. Schulze, M. Stehli
In this paper we will present a multi-stage scheduling approach to generate robust schedules for a challenging aspect of semiconductor manufacturing called time-link areas. A time-link is a technologically induced time constraint between one or more consecutive process steps requiring the process steps to be executed within a predefined time window. Time-links are often introduced to control contamination or unwanted oxidation. Violating time-link constraints may lead to extra effort due to additional rework steps and may have negative yield impact or may even, result in scrap.
{"title":"A Robust Multi-Stage Scheduling Approach for Semiconductor Manufacturing Production Areas with Time Contraints","authors":"Christian Maleck, Gottfried Nieke, K. Bock, Detlef Pabst, M. Schulze, M. Stehli","doi":"10.1109/ASMC.2019.8791779","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791779","url":null,"abstract":"In this paper we will present a multi-stage scheduling approach to generate robust schedules for a challenging aspect of semiconductor manufacturing called time-link areas. A time-link is a technologically induced time constraint between one or more consecutive process steps requiring the process steps to be executed within a predefined time window. Time-links are often introduced to control contamination or unwanted oxidation. Violating time-link constraints may lead to extra effort due to additional rework steps and may have negative yield impact or may even, result in scrap.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131493401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791784
V. Brouzet, V. Gredy, F. Chenevas-Paule, K. Le-Chao, D. Guiheux, A. Laurent, V. Coutellier, D. Le-Cunff
With the introduction of new materials in Back-End of Lines to overcome the development of new options in mature technologies, controlling the local stress and establishing its potential impact on yield becomes more and more critical. In the same way, for high volume production control, it is also important to verify that process equipments of the same kind actually deliver the same materials characteristics as well as to identify which hardware parameters of the process equipment itself can influence the resulting film properties. In this context, this paper will demonstrate how metrology techniques can provide relevant and rapid information on the stress characteristic at the deposition process step itself. This will be illustrated by exploring the impact of wafer centering in a Chemical Vapor Deposition (CVD) dielectric deposition chamber for the case of final Nitride passivation layer both on blanket and product wafers.
{"title":"Full Wafer Stress Metrology for Dielectric Film Characterization: Use Case","authors":"V. Brouzet, V. Gredy, F. Chenevas-Paule, K. Le-Chao, D. Guiheux, A. Laurent, V. Coutellier, D. Le-Cunff","doi":"10.1109/ASMC.2019.8791784","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791784","url":null,"abstract":"With the introduction of new materials in Back-End of Lines to overcome the development of new options in mature technologies, controlling the local stress and establishing its potential impact on yield becomes more and more critical. In the same way, for high volume production control, it is also important to verify that process equipments of the same kind actually deliver the same materials characteristics as well as to identify which hardware parameters of the process equipment itself can influence the resulting film properties. In this context, this paper will demonstrate how metrology techniques can provide relevant and rapid information on the stress characteristic at the deposition process step itself. This will be illustrated by exploring the impact of wafer centering in a Chemical Vapor Deposition (CVD) dielectric deposition chamber for the case of final Nitride passivation layer both on blanket and product wafers.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127929596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791803
S. J. Yoon, Jongwoo Park, A. Kim
Inductively coupled plasma technology is widely used for photoresist strip processes in the modern semiconductor industry. We examined plasma discharge behavior according to various gas mixtures and end capacitance values. Antenna voltage and plasma impedance were measured during plasma discharge. Plasma harmonic was experimentally compared by adjusting the antenna balance. We report the experimental results which reveal that the changes in antenna voltage is associated with the applied gases and their mixing ratio.
{"title":"Optimizing antenna voltage balancing for remote helical ICP plasma discharge using Oxygen, Hydrogen, Nitrogen, Ammonia and their mixtures : AEPM: Advanced Equipment Processes and Materials","authors":"S. J. Yoon, Jongwoo Park, A. Kim","doi":"10.1109/ASMC.2019.8791803","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791803","url":null,"abstract":"Inductively coupled plasma technology is widely used for photoresist strip processes in the modern semiconductor industry. We examined plasma discharge behavior according to various gas mixtures and end capacitance values. Antenna voltage and plasma impedance were measured during plasma discharge. Plasma harmonic was experimentally compared by adjusting the antenna balance. We report the experimental results which reveal that the changes in antenna voltage is associated with the applied gases and their mixing ratio.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128000520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791752
Armando Anaya, William Henning, Neeta Basantkumar, James Oliver
We are living in an era in which data is growing in an exponential pace and coming from multiple sources. This type of data has been called "Big Data". Big data has large volume, variety of formats, high dimensionality and the need for a high speed processing. Those features differentiates it from traditional datasets. Hence data management, analysis, visualization and results communications are getting more complex. The potential of obtaining greater knowledge and more actionable conclusions makes it very attractive. Therefore a data-driven mindset is emerging in different industries and the semiconductor industry is not an exception.This paper describes the results for yield improvement of our silicon carbide technology using advanced data analytics. In doing so, the paper outlines how the data was collected, managed and preprocessed to make it suitable for analysis. It explains which methods and algorithms were used to explore the data, uncover patterns and identify the most important features/predictors.At the end, challenges and conclusions are presented.
{"title":"Yield Improvement Using Advanced Data Analytics","authors":"Armando Anaya, William Henning, Neeta Basantkumar, James Oliver","doi":"10.1109/ASMC.2019.8791752","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791752","url":null,"abstract":"We are living in an era in which data is growing in an exponential pace and coming from multiple sources. This type of data has been called \"Big Data\". Big data has large volume, variety of formats, high dimensionality and the need for a high speed processing. Those features differentiates it from traditional datasets. Hence data management, analysis, visualization and results communications are getting more complex. The potential of obtaining greater knowledge and more actionable conclusions makes it very attractive. Therefore a data-driven mindset is emerging in different industries and the semiconductor industry is not an exception.This paper describes the results for yield improvement of our silicon carbide technology using advanced data analytics. In doing so, the paper outlines how the data was collected, managed and preprocessed to make it suitable for analysis. It explains which methods and algorithms were used to explore the data, uncover patterns and identify the most important features/predictors.At the end, challenges and conclusions are presented.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"44 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131145471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791793
V. Chan, M. Bergendahl, J. Strane, B. Austin, C. Boye, S. Mattam, S. Choi, A. Gaul, K. Cheng, A. Greene, D. Lea, T. Levin, G. Karve, S. Teehan, D. Guo
Ring oscillators (ROs) are used for yield learning during the research phase of a CMOS technology generation. Based on electrical data and binning methods, we improve detection and classification fault methodologies and form a yield detractor pareto. Inline defect monitoring can help to estimate RO yield and is essential in CMOS technology research.
{"title":"Failure Isolation in Ring Oscillator Circuit and Defect Detection in CMOS Technology Research","authors":"V. Chan, M. Bergendahl, J. Strane, B. Austin, C. Boye, S. Mattam, S. Choi, A. Gaul, K. Cheng, A. Greene, D. Lea, T. Levin, G. Karve, S. Teehan, D. Guo","doi":"10.1109/ASMC.2019.8791793","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791793","url":null,"abstract":"Ring oscillators (ROs) are used for yield learning during the research phase of a CMOS technology generation. Based on electrical data and binning methods, we improve detection and classification fault methodologies and form a yield detractor pareto. Inline defect monitoring can help to estimate RO yield and is essential in CMOS technology research.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132144371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791755
Huaxing Tang, Manish Sharma, Wu-Tung Cheng, Gaurav Veda, Douglas D. Gehringer, Matt Knowles, Jayant D'Souza, Kannan Sekar, Neerja Bawaskar, Yan Pan
Device complexity is reaching all-time highs with the adoption of high aspect ratio FinFETs created using multi- patterning process technologies. Simultaneously, new product segments such as AI and automotive are being fabricated on such advanced processes. In this dynamic environment, new complex defect modes have challenged manufacturers to ramp and sustain quality and yield at advanced nodes. Process variability of the standard cell introduces new transistor-level defect modes. Meanwhile the cost of traditional failure analysis has continued to skyrocket. How will the industry reduce the defect-rate and ramp yield to meet these aggressive market demands? This article will detail a new breakthrough in the field of scan diagnosis using machine learning. For the first time, cell-internal defects are detected, diagnosed and now resolved with RCD (Root Cause Deconvolution). Experimental FA results will show how RCD is used to build an accurate defect pareto and pick targeted die for FA for faster and cheaper root cause identification.
{"title":"Yield Learning for Complex FinFET Defect Mechanisms Based on Volume Scan Diagnosis Results","authors":"Huaxing Tang, Manish Sharma, Wu-Tung Cheng, Gaurav Veda, Douglas D. Gehringer, Matt Knowles, Jayant D'Souza, Kannan Sekar, Neerja Bawaskar, Yan Pan","doi":"10.1109/ASMC.2019.8791755","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791755","url":null,"abstract":"Device complexity is reaching all-time highs with the adoption of high aspect ratio FinFETs created using multi- patterning process technologies. Simultaneously, new product segments such as AI and automotive are being fabricated on such advanced processes. In this dynamic environment, new complex defect modes have challenged manufacturers to ramp and sustain quality and yield at advanced nodes. Process variability of the standard cell introduces new transistor-level defect modes. Meanwhile the cost of traditional failure analysis has continued to skyrocket. How will the industry reduce the defect-rate and ramp yield to meet these aggressive market demands? This article will detail a new breakthrough in the field of scan diagnosis using machine learning. For the first time, cell-internal defects are detected, diagnosed and now resolved with RCD (Root Cause Deconvolution). Experimental FA results will show how RCD is used to build an accurate defect pareto and pick targeted die for FA for faster and cheaper root cause identification.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123133591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791772
M. Hagmann, J. Wiedemeier
A new type of scanning probe microscopy is described showing promise for true sub-nanometer resolution in carrier profiling which is essential in failure analysis at and below the 7-nm technology node. The sample resistivity is determined by measuring the attenuation of low-noise attowatt microwave signals generated in a tunneling junction by optical rectification.
{"title":"Scanning Frequency Comb Microscopy (SFCM) Shows Promise for Carrier Profiling at and Below the 7-nm Node","authors":"M. Hagmann, J. Wiedemeier","doi":"10.1109/ASMC.2019.8791772","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791772","url":null,"abstract":"A new type of scanning probe microscopy is described showing promise for true sub-nanometer resolution in carrier profiling which is essential in failure analysis at and below the 7-nm technology node. The sample resistivity is determined by measuring the attenuation of low-noise attowatt microwave signals generated in a tunneling junction by optical rectification.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134604749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791764
N. Chaudhary, S. Savari
We propose deep convolutional neural networks LineNet1 and LineNet2 for simultaneous denoising and edge image prediction from low-dose scanning electron microscope images. Edge estimation of nanostructures from SEM images is needed for line edge roughness (LER) and line width roughness (LWR) estimation. Our method uses supervised learning datasets of single-line SEM images and multiple-line SEM images together with edge positions information for the training of LineNet1 and LineNet2. We simulate single-line and multiple-line SEM images with Poisson noise and other artifacts using the ARTIMAGEN library developed by the National Institute of Standards and Technology. The line edges were generated using the Thorsos method and the Palasantzas spectral model. The convolutional neural networks LineNet1 and LineNet2 each contain 17 con- volutional layers, 16 batch-normalization layers and 16 dropout layers. Our results show that this approach (1) facilitates edge estimation in multiple-line images and (2) significantly reduces the memory needed for edge estimation in single-line images with a slight impact on accuracy.
{"title":"Simultaneous Denoising and Edge Estimation from SEM Images using Deep Convolutional Neural Networks","authors":"N. Chaudhary, S. Savari","doi":"10.1109/ASMC.2019.8791764","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791764","url":null,"abstract":"We propose deep convolutional neural networks LineNet1 and LineNet2 for simultaneous denoising and edge image prediction from low-dose scanning electron microscope images. Edge estimation of nanostructures from SEM images is needed for line edge roughness (LER) and line width roughness (LWR) estimation. Our method uses supervised learning datasets of single-line SEM images and multiple-line SEM images together with edge positions information for the training of LineNet1 and LineNet2. We simulate single-line and multiple-line SEM images with Poisson noise and other artifacts using the ARTIMAGEN library developed by the National Institute of Standards and Technology. The line edges were generated using the Thorsos method and the Palasantzas spectral model. The convolutional neural networks LineNet1 and LineNet2 each contain 17 con- volutional layers, 16 batch-normalization layers and 16 dropout layers. Our results show that this approach (1) facilitates edge estimation in multiple-line images and (2) significantly reduces the memory needed for edge estimation in single-line images with a slight impact on accuracy.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115794226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791809
Asli Sirman, Fuad H. Al-amoody, Chandar Palamadai, B. Saville, Ankit Jain, Kha X. Tran
This paper describes a novel methodology for identifying pinholes (defects in thin films) in an amorphous silicon (a-Si) film using a KLA Surfscan® SP5 laser scattering-based unpatterned wafer inspection system. Inherent to the deposition mechanism, pinholes exist at the interface between a-Si/substrate. It is crucial to find the optimized film thickness that is free of pinholes. In this study we developed a unique process monitoring method adapted to quantify pinhole defects using surface haze. Haze is the background scattering signal of the wafer obtained from the inspection system [1] and the defect signal from scanning electron microscope (SEM) images from an eDR® e-beam defect review system. A macro program was developed to automatically process the SEM images and quantify the defect signal. A strong correlation between haze and a-Si pinhole count was observed. The method can be extended to different films including SiN, TiN and similar scenarios, where unconventional defect detection methods are needed.
{"title":"a-Si Pinhole Detection and Characterization using Haze Monitoring : CFM: Contamination Free Manufacturing","authors":"Asli Sirman, Fuad H. Al-amoody, Chandar Palamadai, B. Saville, Ankit Jain, Kha X. Tran","doi":"10.1109/ASMC.2019.8791809","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791809","url":null,"abstract":"This paper describes a novel methodology for identifying pinholes (defects in thin films) in an amorphous silicon (a-Si) film using a KLA Surfscan® SP5 laser scattering-based unpatterned wafer inspection system. Inherent to the deposition mechanism, pinholes exist at the interface between a-Si/substrate. It is crucial to find the optimized film thickness that is free of pinholes. In this study we developed a unique process monitoring method adapted to quantify pinhole defects using surface haze. Haze is the background scattering signal of the wafer obtained from the inspection system [1] and the defect signal from scanning electron microscope (SEM) images from an eDR® e-beam defect review system. A macro program was developed to automatically process the SEM images and quantify the defect signal. A strong correlation between haze and a-Si pinhole count was observed. The method can be extended to different films including SiN, TiN and similar scenarios, where unconventional defect detection methods are needed.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"285 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116106748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/ASMC.2019.8791771
B. Duclaux, A. Pelletier, J. de-Caunes, R. Perrier, L. Babaud, M. Gatefait, Olivier Fagart, Nicolas Thivolle, Mathieu Guerabsi, J. Chapon, Bruno Perrin, C. Monget
I.IntroductionWith overlay requirements getting more and more critical, a lot of work has been done in the industry to improve the overlay correction capability by using high order process corrections, corrections per exposure and heating control (lens and reticle). Another part of the overlay budget is linked to our ability to control and stabilize it through time as well as being reactive to changes via the advanced process control system of the fab (APC)[1]. This paper describes the steps taken from an individual feedback loops configuration (one technology, one or several similar layers) to large perimeter overlay run- to-run for a high-mix 300mm semiconductor logic fab[2]. First, a multivariate APC system is defined with all the specificities needed to enable a large perimeter configuration. Then, technology/layer grouping is explained as well as filters and limits settings to start the new feedback loops simulation. The simulation phase or "learning mode" allows to have an overview on the expected gains: enhanced reactivity to parameters drift and easier maintenance by engineers in charge of following overlay run-to-run, which indirectly leads to better overall APC performance. After overlay large perimeter activation, the alert number drastically decreases, risk of measurement sampling is minimized in the fab and a similar approach is started on energy large perimeter (CD: Critical Dimensions).
{"title":"Convergence towards large perimeter overlay Run-to-Run using multivariate APC system","authors":"B. Duclaux, A. Pelletier, J. de-Caunes, R. Perrier, L. Babaud, M. Gatefait, Olivier Fagart, Nicolas Thivolle, Mathieu Guerabsi, J. Chapon, Bruno Perrin, C. Monget","doi":"10.1109/ASMC.2019.8791771","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791771","url":null,"abstract":"I.IntroductionWith overlay requirements getting more and more critical, a lot of work has been done in the industry to improve the overlay correction capability by using high order process corrections, corrections per exposure and heating control (lens and reticle). Another part of the overlay budget is linked to our ability to control and stabilize it through time as well as being reactive to changes via the advanced process control system of the fab (APC)[1]. This paper describes the steps taken from an individual feedback loops configuration (one technology, one or several similar layers) to large perimeter overlay run- to-run for a high-mix 300mm semiconductor logic fab[2]. First, a multivariate APC system is defined with all the specificities needed to enable a large perimeter configuration. Then, technology/layer grouping is explained as well as filters and limits settings to start the new feedback loops simulation. The simulation phase or \"learning mode\" allows to have an overview on the expected gains: enhanced reactivity to parameters drift and easier maintenance by engineers in charge of following overlay run-to-run, which indirectly leads to better overall APC performance. After overlay large perimeter activation, the alert number drastically decreases, risk of measurement sampling is minimized in the fab and a similar approach is started on energy large perimeter (CD: Critical Dimensions).","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127663370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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