Pub Date : 2005-06-22DOI: 10.1109/DRC.2005.1553072
A. Chao, P. Kapur, R. Shenoy, Y. Nishi, K. Saraswat
In this work, we extend this methodology to include the impact of supply voltage and process parameter variations (gate length, Lg , body thickness, Tsi). A variation-aware methodology yields a realistic comparison between different device technology options at the future nodes. In addition, it gives a more measured assessment of both the minimum power possible as well as the optimal voltage-scaling roadmap. We show the efficacy and the wide scope of this methodology by applying it to a myriad of transistor related applications
{"title":"Incorporation of supply voltage and process variations in the power optimization for future transistors","authors":"A. Chao, P. Kapur, R. Shenoy, Y. Nishi, K. Saraswat","doi":"10.1109/DRC.2005.1553072","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553072","url":null,"abstract":"In this work, we extend this methodology to include the impact of supply voltage and process parameter variations (gate length, Lg , body thickness, Tsi). A variation-aware methodology yields a realistic comparison between different device technology options at the future nodes. In addition, it gives a more measured assessment of both the minimum power possible as well as the optimal voltage-scaling roadmap. We show the efficacy and the wide scope of this methodology by applying it to a myriad of transistor related applications","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":"419 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131783097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-22DOI: 10.1109/DRC.2005.1553085
K. Yadavalli, A. Orlov, R. Kummamuru, C. Lent, G. Bernstein, G. Snider
In this report, we describe the fabrication and experimental demonstration of fanout in QCA. Fanout is important as it is necessary for complex digital logic circuits and is essential for generating compact designs, as multiple cells can be then driven by a single driver cell. Fanout in QCA is also a direct demonstration of power gain in QCA circuits. The device is realized using metal islands (as quantum dots) and multiple tunnel junctions (MTJs) fabricated using Dolan bridge technique (Fulton, 1987). The circuit consists of three latches, with the latch in the first stage (L1) capacitively coupled to the two latches of the second stage (L2 and L3). The goal of the experiment is to switch L2 and L3 simultaneously using L1 as an input driving both L2 and L3. Each latch is formed by three quantum dots with the middle dot being connected to the end dots by MTJs
{"title":"Fanout in quantum dot cellular automata","authors":"K. Yadavalli, A. Orlov, R. Kummamuru, C. Lent, G. Bernstein, G. Snider","doi":"10.1109/DRC.2005.1553085","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553085","url":null,"abstract":"In this report, we describe the fabrication and experimental demonstration of fanout in QCA. Fanout is important as it is necessary for complex digital logic circuits and is essential for generating compact designs, as multiple cells can be then driven by a single driver cell. Fanout in QCA is also a direct demonstration of power gain in QCA circuits. The device is realized using metal islands (as quantum dots) and multiple tunnel junctions (MTJs) fabricated using Dolan bridge technique (Fulton, 1987). The circuit consists of three latches, with the latch in the first stage (L1) capacitively coupled to the two latches of the second stage (L2 and L3). The goal of the experiment is to switch L2 and L3 simultaneously using L1 as an input driving both L2 and L3. Each latch is formed by three quantum dots with the middle dot being connected to the end dots by MTJs","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":"164 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127410437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-22DOI: 10.1109/DRC.2005.1553113
J. Cooper, Y. Sui, X. Wang, G. Walden
Silicon carbide power switching devices have made remarkable progress in the past decade. As blocking voltage increases, the resistance of power switches becomes dominated by the drift region, and the advantage of SiC over silicon increases. This is illustrated by the degree to which SiC unipolar devices are approaching their theoretical limits at blocking voltages around 10 kV. Efforts are currently underway to develop power switching devices for the 15-25 kV regime
{"title":"Device options for high-voltage SiC power switching devices","authors":"J. Cooper, Y. Sui, X. Wang, G. Walden","doi":"10.1109/DRC.2005.1553113","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553113","url":null,"abstract":"Silicon carbide power switching devices have made remarkable progress in the past decade. As blocking voltage increases, the resistance of power switches becomes dominated by the drift region, and the advantage of SiC over silicon increases. This is illustrated by the degree to which SiC unipolar devices are approaching their theoretical limits at blocking voltages around 10 kV. Efforts are currently underway to develop power switching devices for the 15-25 kV regime","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133768495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-22DOI: 10.1109/DRC.2005.1553120
K. Shin, T. Lauderdale, T. King
Strained-silicon technologies have been widely investigated to enhance the performance of CMOS devices (Thompson, et. al., 2005). In particular, strain induced by the use of a stressed SiNx capping layer is advantageous because of its process simplicity and its extendibility from bulk-Si to silicon-on-insulator (SOI) MOSFETs (Komoda, 2004, Pidin, 2004). In this paper, the effect of a tensile capping layer on the stress profile in the channel of a FinFET is studied for different channel-surface crystalline orientations and different fin aspect ratios, using the Ansys5.7 simulator
{"title":"Effect of tensile capping layer on 3-D stress profiles in FinFET channels","authors":"K. Shin, T. Lauderdale, T. King","doi":"10.1109/DRC.2005.1553120","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553120","url":null,"abstract":"Strained-silicon technologies have been widely investigated to enhance the performance of CMOS devices (Thompson, et. al., 2005). In particular, strain induced by the use of a stressed SiNx capping layer is advantageous because of its process simplicity and its extendibility from bulk-Si to silicon-on-insulator (SOI) MOSFETs (Komoda, 2004, Pidin, 2004). In this paper, the effect of a tensile capping layer on the stress profile in the channel of a FinFET is studied for different channel-surface crystalline orientations and different fin aspect ratios, using the Ansys5.7 simulator","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124262071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-22DOI: 10.1109/DRC.2005.1553043
H. Chae, Y. Jung, S. Seo, J. Han, J. Hyun, G. W. Park, M.Y. Um, J. Kim, B.J. Lee, K. Kim, J. cho, G. Bae, N. Lee, S. Kang, C.W. Kim
In this paper, data retention loss phenomena after write/erase cycles and time in an embedded SONOS memory cell were investigated for the first time. By analyzing source junction leakage current, it was determined that the loss of holes in nitride also results in an increase in threshold voltage, a drop in ion, and a degradation of sub-threshold slope
{"title":"Data retention behavior in the embedded SONOS nonvolatile memory cell","authors":"H. Chae, Y. Jung, S. Seo, J. Han, J. Hyun, G. W. Park, M.Y. Um, J. Kim, B.J. Lee, K. Kim, J. cho, G. Bae, N. Lee, S. Kang, C.W. Kim","doi":"10.1109/DRC.2005.1553043","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553043","url":null,"abstract":"In this paper, data retention loss phenomena after write/erase cycles and time in an embedded SONOS memory cell were investigated for the first time. By analyzing source junction leakage current, it was determined that the loss of holes in nitride also results in an increase in threshold voltage, a drop in ion, and a degradation of sub-threshold slope","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114403874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-22DOI: 10.1109/DRC.2005.1553056
A. Chini, S. Rajan, M. Wong, Y. Fu, J. Speck, U. Mishra
The paper reports on the characteristics of N-face AlGaN/GaN/AlGaN HEMTs. Ohmic contact optmization experiments based on the Ti/Al/Ni/Au metallization scheme commonly used for Ga-face AlGaN/GaN HEMTs were carried out and a low contact resistance of 1.3 Ohm/mm was achieved. The devices were then characterized before and after SiN passivation. Before passivation, large current dispersion was observed in 80mus pulsed I-V measurements compare to the DC I-V curves. The adoption of a SiN passivation layer improved the I-V pulsed characteristics at 80mus but current dispersion was still severe when using shorter (200ns) pulse widths
{"title":"Fabrication and characterization of N-face AlGaN/GaN/AlGaN HEMTs","authors":"A. Chini, S. Rajan, M. Wong, Y. Fu, J. Speck, U. Mishra","doi":"10.1109/DRC.2005.1553056","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553056","url":null,"abstract":"The paper reports on the characteristics of N-face AlGaN/GaN/AlGaN HEMTs. Ohmic contact optmization experiments based on the Ti/Al/Ni/Au metallization scheme commonly used for Ga-face AlGaN/GaN HEMTs were carried out and a low contact resistance of 1.3 Ohm/mm was achieved. The devices were then characterized before and after SiN passivation. Before passivation, large current dispersion was observed in 80mus pulsed I-V measurements compare to the DC I-V curves. The adoption of a SiN passivation layer improved the I-V pulsed characteristics at 80mus but current dispersion was still severe when using shorter (200ns) pulse widths","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129022635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-22DOI: 10.1109/DRC.2005.1553052
H. Cha, Xiaodong Chen, W. Schaff, M. Spencer, L. Eastman, B. Ridley, J. Pomeroy, M. Kuball
In order to achieve operation at terahertz frequency, electronic devices are required to reach the highest possible transit velocity, even if this velocity is limited to a short distance. The concept of ballistic electrons in compound semiconductors was initially reported using GaAs (Shur and Eastman, 1979). In this work, progress in initial research on GaN based ballistic electron acceleration negative-differential-conductivity (BEAN) diodes for potential THz oscillator is reported along with their device concepts
为了实现在太赫兹频率下的工作，电子设备需要达到尽可能高的传输速度，即使这个速度被限制在很短的距离内。化合物半导体中弹道电子的概念最初是用砷化镓(Shur and Eastman, 1979)报道的。在这项工作中，报告了GaN基弹道电子加速负微分电导率(BEAN)二极管的初步研究进展及其器件概念
{"title":"Gallium nitride based ballistic electron acceleration negativedifferentialconductivity diodes for potential THZ applications","authors":"H. Cha, Xiaodong Chen, W. Schaff, M. Spencer, L. Eastman, B. Ridley, J. Pomeroy, M. Kuball","doi":"10.1109/DRC.2005.1553052","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553052","url":null,"abstract":"In order to achieve operation at terahertz frequency, electronic devices are required to reach the highest possible transit velocity, even if this velocity is limited to a short distance. The concept of ballistic electrons in compound semiconductors was initially reported using GaAs (Shur and Eastman, 1979). In this work, progress in initial research on GaN based ballistic electron acceleration negative-differential-conductivity (BEAN) diodes for potential THz oscillator is reported along with their device concepts","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126570530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-22DOI: 10.1109/DRC.2005.1553119
Wei Zhao, A. Seabaugh, B. Winstead, D. Jovanovic, V. Adams
In this paper, we report the first investigation of the influence of uniaxial tensile strain on the gate tunneling current in advanced partially-depleted silicon-on-insulator (PD-SOI) MOSFETs. We have also studied, for the first time, the impact of uniaxial strain on the static leakage current of ring oscillators (RO) fabricated in this technology
{"title":"Impact of uniaxial strain on the gate leakage currents of PD-SOI MOSFETs and ring oscillators with ultra-thin gate dielectric","authors":"Wei Zhao, A. Seabaugh, B. Winstead, D. Jovanovic, V. Adams","doi":"10.1109/DRC.2005.1553119","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553119","url":null,"abstract":"In this paper, we report the first investigation of the influence of uniaxial tensile strain on the gate tunneling current in advanced partially-depleted silicon-on-insulator (PD-SOI) MOSFETs. We have also studied, for the first time, the impact of uniaxial strain on the static leakage current of ring oscillators (RO) fabricated in this technology","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121281614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-22DOI: 10.1109/DRC.2005.1553106
K. Alam, R. Lake
We consider a 1.5 nm diameter (19,0) CNT for which zero-Schottky-barrier contacts have been demonstrated. The model device has a wrap-around gate, 2 nm ZrO2 dielectric, and the Fermi level of the metal contacts aligned with the conduction band of the source and drain. A number of different CNT lengths with various source/drain asymmetry are studied. A 40 nm length CNT with a 10 nm gate shows excellent performance as quantified below. We numerically calculate the gate delay (taus = C9VDD/ION), ON/OFF current ratio, and inverse subthreshold slope as a function of source to gate underlap L exS
{"title":"Optimal design and coulomb blockade suppressed leakage of carbon nanotube transistors","authors":"K. Alam, R. Lake","doi":"10.1109/DRC.2005.1553106","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553106","url":null,"abstract":"We consider a 1.5 nm diameter (19,0) CNT for which zero-Schottky-barrier contacts have been demonstrated. The model device has a wrap-around gate, 2 nm ZrO2 dielectric, and the Fermi level of the metal contacts aligned with the conduction band of the source and drain. A number of different CNT lengths with various source/drain asymmetry are studied. A 40 nm length CNT with a 10 nm gate shows excellent performance as quantified below. We numerically calculate the gate delay (taus = C9VDD/ION), ON/OFF current ratio, and inverse subthreshold slope as a function of source to gate underlap L exS","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":"9 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132286307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-22DOI: 10.1109/DRC.2005.1553046
Yueran Liu, S. Tang, Decai Yu, G. Hwang, S. Banerjee
For nonvolatile memory devices, a long retention time is very important. Nanocrystal floating gate has been demonstrated to lead to an improvement for retention time compare to conventional continuous floating gate. In this paper, the authors present our studies of activation energy for SiGe nanocrystal flash memory devices as a function of tunnel oxide thickness to try to clarify this issue
{"title":"Tunnel oxide thickness dependence of activation energy for SiGe quantum dot flash memory","authors":"Yueran Liu, S. Tang, Decai Yu, G. Hwang, S. Banerjee","doi":"10.1109/DRC.2005.1553046","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553046","url":null,"abstract":"For nonvolatile memory devices, a long retention time is very important. Nanocrystal floating gate has been demonstrated to lead to an improvement for retention time compare to conventional continuous floating gate. In this paper, the authors present our studies of activation energy for SiGe nanocrystal flash memory devices as a function of tunnel oxide thickness to try to clarify this issue","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124812215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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