Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830518
Gregory K. Chen, Phil C. Knag, Carlos Tokunaga, R. Krishnamurthy
An 8-core 64b processor extends RISC-V to perform multiply accumulate within shared last level cache. Compute Near Last Level Cache (CNC) enables high-bandwidth access and local compute with the highest-capacity on-chip SRAM. The 1.15GHz chip expands virtual addressing, coherency, and consistency to CNC, enabling Linux-capable multi-core operation. CNC reduces energy by 52× for fully connected and 29× for convolutional DNN layers. MLPerf™ Anomaly Detection latency is reduced by 4.25× to 40μs.
{"title":"An 8-core RISC-V Processor with Compute near Last Level Cache in Intel 4 CMOS","authors":"Gregory K. Chen, Phil C. Knag, Carlos Tokunaga, R. Krishnamurthy","doi":"10.1109/vlsitechnologyandcir46769.2022.9830518","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830518","url":null,"abstract":"An 8-core 64b processor extends RISC-V to perform multiply accumulate within shared last level cache. Compute Near Last Level Cache (CNC) enables high-bandwidth access and local compute with the highest-capacity on-chip SRAM. The 1.15GHz chip expands virtual addressing, coherency, and consistency to CNC, enabling Linux-capable multi-core operation. CNC reduces energy by 52× for fully connected and 29× for convolutional DNN layers. MLPerf™ Anomaly Detection latency is reduced by 4.25× to 40μs.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127469506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830242
W.-C. Chen, F. Huang, S. Qin, Z. Yu, Q. Lin, P. McIntyre, S. Wong, H. P. Wong
We present 1-FeFET-1-RRAM (1F1R) hybrid nonvolatile memory for dense embedded memory application. By allocating 2 bits each in the RRAM and FeFET, we show 4 bits/cell capability with retention over 104 seconds at 85 °C. An array of 1F1R cells enables a new compute-in-memory (CIM) concept – Masked CIM. Masked CIM can store 2× the amount of signed weights compared with traditional CIM array. Doubling synapses density allows implementing larger neural network models that is critical for applications beyond toy datasets such as MNIST or CIFAR-10.
{"title":"4 Bits/cell Hybrid 1F1R for High Density Embedded Non-Volatile Memory and its Application for Compute in Memory","authors":"W.-C. Chen, F. Huang, S. Qin, Z. Yu, Q. Lin, P. McIntyre, S. Wong, H. P. Wong","doi":"10.1109/vlsitechnologyandcir46769.2022.9830242","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830242","url":null,"abstract":"We present 1-FeFET-1-RRAM (1F1R) hybrid nonvolatile memory for dense embedded memory application. By allocating 2 bits each in the RRAM and FeFET, we show 4 bits/cell capability with retention over 104 seconds at 85 °C. An array of 1F1R cells enables a new compute-in-memory (CIM) concept – Masked CIM. Masked CIM can store 2× the amount of signed weights compared with traditional CIM array. Doubling synapses density allows implementing larger neural network models that is critical for applications beyond toy datasets such as MNIST or CIFAR-10.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125050063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830151
H. Shin, Sangkyung Won, Do-Hee Kim, Byung-Soon Choi, G.H. Kim, Myeonghee Oh, Jaeseung Choi, J. Kye
A 28nm embedded Flash memory presented in this paper maximizes memory operation efficiently while implementing an optimal size. The peripheral size was reduced by applying the temperature auto tracking assist circuit with Bidirectional and Series-Parallel Conversion (BSPC) charge pump technology, and the IP size was improved by implementing the maximum density per mat by enhancing the sensing margin using Source Line Floating (SLF) technology. Also, using Program Current Auto Control (PCAC) scheme, program operation efficiency was improved and characteristic deviation of bit cell was reduced. With the application of these technologies, 72 bits program and 144 bits read operation are supported, and chip size 2.367mm2 is implemented based on 32Mbit density. This has the best competitiveness considering the area Mbit (13.48Mb/mm2) and Cell efficiency (68.1%).
{"title":"A 32Mb Embedded Flash Memory based on 28nm with the best Cell Efficiency and Robust Design achievement featuring 13.48Mb/mm2 at 0.85V","authors":"H. Shin, Sangkyung Won, Do-Hee Kim, Byung-Soon Choi, G.H. Kim, Myeonghee Oh, Jaeseung Choi, J. Kye","doi":"10.1109/vlsitechnologyandcir46769.2022.9830151","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830151","url":null,"abstract":"A 28nm embedded Flash memory presented in this paper maximizes memory operation efficiently while implementing an optimal size. The peripheral size was reduced by applying the temperature auto tracking assist circuit with Bidirectional and Series-Parallel Conversion (BSPC) charge pump technology, and the IP size was improved by implementing the maximum density per mat by enhancing the sensing margin using Source Line Floating (SLF) technology. Also, using Program Current Auto Control (PCAC) scheme, program operation efficiency was improved and characteristic deviation of bit cell was reduced. With the application of these technologies, 72 bits program and 144 bits read operation are supported, and chip size 2.367mm2 is implemented based on 32Mbit density. This has the best competitiveness considering the area Mbit (13.48Mb/mm2) and Cell efficiency (68.1%).","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125196225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830450
Giyoung Yang, Hakchul Jung, J. Lim, Jaewoo Seo, Ingyum Kim, Jisun Yu, H. You, Jeongsoon Kong, Garoom Kim, Minjae Jeong, Chanhee Park, Sera An, W. Rim, Hayoung Kim, Dalhee Lee, S. Baek, Jonghoon Jung, T. Song, J. Kye
In this paper, standard cell design challenges for the 3nm process are introduced, solved, and optimized using the advanced MOL technology, AC P–N connection. In this methodology, each drain nodes of P and NMOS are connected using a single MOL layer (AC). Utilizing the AC P–N connection, standard cell library can be improved in three different ways. First, reduce the parasitic wire resistance by more than 20% and improve circuit reliability by alleviating a high current density. Second, Ceff improvement by composing only the MOL layer (AC) for the output node of the cell improves the standard cell speed up to 9.6%. Third, we propose a novel Flip-Flop (FF) structure optimized for AC P–N connection, thus improving the speed of the FF (1/TD2Q) by 9.1%.
{"title":"Standard Cell Design Optimization with Advanced MOL Technology in 3nm GAA Process","authors":"Giyoung Yang, Hakchul Jung, J. Lim, Jaewoo Seo, Ingyum Kim, Jisun Yu, H. You, Jeongsoon Kong, Garoom Kim, Minjae Jeong, Chanhee Park, Sera An, W. Rim, Hayoung Kim, Dalhee Lee, S. Baek, Jonghoon Jung, T. Song, J. Kye","doi":"10.1109/vlsitechnologyandcir46769.2022.9830450","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830450","url":null,"abstract":"In this paper, standard cell design challenges for the 3nm process are introduced, solved, and optimized using the advanced MOL technology, AC P–N connection. In this methodology, each drain nodes of P and NMOS are connected using a single MOL layer (AC). Utilizing the AC P–N connection, standard cell library can be improved in three different ways. First, reduce the parasitic wire resistance by more than 20% and improve circuit reliability by alleviating a high current density. Second, Ceff improvement by composing only the MOL layer (AC) for the output node of the cell improves the standard cell speed up to 9.6%. Third, we propose a novel Flip-Flop (FF) structure optimized for AC P–N connection, thus improving the speed of the FF (1/TD2Q) by 9.1%.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123632859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830225
H. Fuketa, I. Akita, T. Ishikawa, H. Koike, T. Mori
Employing a precise current readout circuit enabled by a current integrator and correlation double sampling circuit, we propose a cryo-CMOS current comparator circuit to readout spin qubit states by a charge sensing scheme. The reduced readout time by a factor of 1/100 and 100-times better current resolution with the readout fidelity of 99.9% compared to the conventional readout systems are achieved. Furthermore, the proposed current comparator attains the best figure-of-merit (FoM) among the conventional cryogenic current readout circuits. This is the demonstration that cryo-CMOS technology can enhance the performance of quantum computer systems.
{"title":"A Cryogenic CMOS Current Comparator for Spin Qubit Readout Achieving Fast Readout Time and High Current Resolution","authors":"H. Fuketa, I. Akita, T. Ishikawa, H. Koike, T. Mori","doi":"10.1109/vlsitechnologyandcir46769.2022.9830225","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830225","url":null,"abstract":"Employing a precise current readout circuit enabled by a current integrator and correlation double sampling circuit, we propose a cryo-CMOS current comparator circuit to readout spin qubit states by a charge sensing scheme. The reduced readout time by a factor of 1/100 and 100-times better current resolution with the readout fidelity of 99.9% compared to the conventional readout systems are achieved. Furthermore, the proposed current comparator attains the best figure-of-merit (FoM) among the conventional cryogenic current readout circuits. This is the demonstration that cryo-CMOS technology can enhance the performance of quantum computer systems.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123718767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830405
P. Tseng, Yu-Hsuan Lin, F. Lee, Tian-Cig Bo, Yung-Chun Li, Ming-Hsiu Lee, K. Hsieh, Keh-Chung Wang, Chih-Yuan Lu
A high performance 3D-NAND-flash based approximate computing architecture is proposed to execute in-memory similarity computation. This approximate-computing chip features fuzzy in-memory search (IMS) function with ultra-high parallelism at full-block scale in just one read cycle. The system architecture from the IMS unit cell/string/array configuration to the novel approximate comparison scheme are discussed in detail. Practical issues including Vt distribution, retention loss, and read disturbance are evaluated. We also introduce a novel IMS group-encoding scheme, which can significantly increase the content density under the same string length. Face recognition with VGGFace2 dataset is demonstrated with high accuracy and good tolerability on reliability degradation.
{"title":"In-Memory Approximate Computing Architecture Based on 3D-NAND Flash Memories","authors":"P. Tseng, Yu-Hsuan Lin, F. Lee, Tian-Cig Bo, Yung-Chun Li, Ming-Hsiu Lee, K. Hsieh, Keh-Chung Wang, Chih-Yuan Lu","doi":"10.1109/vlsitechnologyandcir46769.2022.9830405","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830405","url":null,"abstract":"A high performance 3D-NAND-flash based approximate computing architecture is proposed to execute in-memory similarity computation. This approximate-computing chip features fuzzy in-memory search (IMS) function with ultra-high parallelism at full-block scale in just one read cycle. The system architecture from the IMS unit cell/string/array configuration to the novel approximate comparison scheme are discussed in detail. Practical issues including Vt distribution, retention loss, and read disturbance are evaluated. We also introduce a novel IMS group-encoding scheme, which can significantly increase the content density under the same string length. Face recognition with VGGFace2 dataset is demonstrated with high accuracy and good tolerability on reliability degradation.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123789205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830181
H. Bae, Jeong-Hyun Cho, Gyeong-Gu Kang, Yousung Park, Hyunsik Kim
This paper presents a fast dynamic voltage scaling (DVS) buck converter without losing high efficiency. The proposed isosceles-triangular shunt current (ITSC) push-pull technique allows a turning-point for optimal DVS to be independent of passive components while supplying sufficient current of 35A/μs. Current-tailing handover (CTH) realizes no voltage droop after DVS even under resistive loads. ITSC and CTH can also enhance load-transient response. The chip fabricated in 180-nm CMOS achieves 7V/μs DVS-rate and 97.6% peak efficiency.
{"title":"A 97.6%-Efficient 1-2MHz Hysteretic Buck Converter with 7V/μs DVS-Rate Enabled by Isosceles-Triangular Shunt Current Push-Pull Technique","authors":"H. Bae, Jeong-Hyun Cho, Gyeong-Gu Kang, Yousung Park, Hyunsik Kim","doi":"10.1109/vlsitechnologyandcir46769.2022.9830181","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830181","url":null,"abstract":"This paper presents a fast dynamic voltage scaling (DVS) buck converter without losing high efficiency. The proposed isosceles-triangular shunt current (ITSC) push-pull technique allows a turning-point for optimal DVS to be independent of passive components while supplying sufficient current of 35A/μs. Current-tailing handover (CTH) realizes no voltage droop after DVS even under resistive loads. ITSC and CTH can also enhance load-transient response. The chip fabricated in 180-nm CMOS achieves 7V/μs DVS-rate and 97.6% peak efficiency.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131459088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830233
Hyunki Han, Min-Woo Ko, Jeong-Hyun Cho, Gyeong-Gu Kang, Seok-Tae Koh, H. Bae, Hyunsik Kim
This paper presents a 48V-to-1V quadruple step-down (QSD) DC-DC converter. The QSD comprising 4 parallel-inductors and 3 series-capacitors can efficiently supply up to 10A with fully monolithic 12V LDMOS by lowering the switching voltage to be quartered. The hysteretic copied on-time (HCOT) control allows clockless synchronization of 4-phase QSD without collapsing series-capacitor voltages. The 2-phase all-hysteretic (2× slew rate) mode is also presented for voltage droop mitigation under extreme load fluctuations. The chip fabricated in 0.18-μm BCD shows a peak efficiency of 88.5% and achieves ∆80mV sag and 1μs 2%-recovery time for a 6.3A/50ns load transition.
{"title":"A Monolithic 48V-to-1V 10A Quadruple Step-Down DC-DC Converter with Hysteretic Copied On-Time 4-Phase Control and 2× Slew Rate All-Hysteretic Mode","authors":"Hyunki Han, Min-Woo Ko, Jeong-Hyun Cho, Gyeong-Gu Kang, Seok-Tae Koh, H. Bae, Hyunsik Kim","doi":"10.1109/vlsitechnologyandcir46769.2022.9830233","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830233","url":null,"abstract":"This paper presents a 48V-to-1V quadruple step-down (QSD) DC-DC converter. The QSD comprising 4 parallel-inductors and 3 series-capacitors can efficiently supply up to 10A with fully monolithic 12V LDMOS by lowering the switching voltage to be quartered. The hysteretic copied on-time (HCOT) control allows clockless synchronization of 4-phase QSD without collapsing series-capacitor voltages. The 2-phase all-hysteretic (2× slew rate) mode is also presented for voltage droop mitigation under extreme load fluctuations. The chip fabricated in 0.18-μm BCD shows a peak efficiency of 88.5% and achieves ∆80mV sag and 1μs 2%-recovery time for a 6.3A/50ns load transition.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126316733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830455
S. Ray, P. Kinget
To alleviate the feature extraction bottleneck in always-on, on-device Keyword Spotting (KWS), we propose two novel analog circuit techniques that are combined into an efficient analog feature extraction architecture: 1) Time-Mode Analog Filterbank Interpolation (TM-AFI) uses digital XOR gates to double the number of outputs of an analog filterbank, 2) Time-Mode Analog Rectification (TM-AR) uses a single digital XOR gate as an analog full-wave rectifier. Among other analog feature extractor chips using a software classifier for a KWS demo, the 31-feature, 80nW, 0.53mm2 prototype is 18× more power-efficient and 3.3× more area-efficient than the most area- and power-efficient published works, respectively, while maintaining competitive >90% accuracy on 10 keywords.
{"title":"A 31-Feature, 80nW, 0.53mm2 Audio Analog Feature Extractor based on Time-Mode Analog Filterbank Interpolation and Time-Mode Analog Rectification","authors":"S. Ray, P. Kinget","doi":"10.1109/vlsitechnologyandcir46769.2022.9830455","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830455","url":null,"abstract":"To alleviate the feature extraction bottleneck in always-on, on-device Keyword Spotting (KWS), we propose two novel analog circuit techniques that are combined into an efficient analog feature extraction architecture: 1) Time-Mode Analog Filterbank Interpolation (TM-AFI) uses digital XOR gates to double the number of outputs of an analog filterbank, 2) Time-Mode Analog Rectification (TM-AR) uses a single digital XOR gate as an analog full-wave rectifier. Among other analog feature extractor chips using a software classifier for a KWS demo, the 31-feature, 80nW, 0.53mm2 prototype is 18× more power-efficient and 3.3× more area-efficient than the most area- and power-efficient published works, respectively, while maintaining competitive >90% accuracy on 10 keywords.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122335007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830150
G. Murdoch, M. O'Toole, G. Marti, A. Pokhrel, D. Tsvetanova, S. Decoster, S. Kundu, Y. Oniki, A. Thiam, Q. T. Le, O. Pedreira, A. Lesniewska, G. Martinez-Alanis, S. Park, Z. Tokei
In this paper we demonstrate the functionality of a semi-damascene integration scheme with fully self-aligned vias (FSAV) for interconnects from 26 to 18nm metal pitch (MP), fabricated on 300mm wafers. We have developed a novel integration flow, using the principle of subtractive etching of Ru, on 2 subsequent metal levels. Using structures with programmed overlay shift, we demonstrate the functionality of a fully self-aligned via process which results in working devices with placement errors of up to 5nm. Furthermore, we show via-to-line breakdown field > 9MV/cm, confirming FSAV.
{"title":"First demonstration of Two Metal Level Semi-damascene Interconnects with Fully Self-aligned Vias at 18MP","authors":"G. Murdoch, M. O'Toole, G. Marti, A. Pokhrel, D. Tsvetanova, S. Decoster, S. Kundu, Y. Oniki, A. Thiam, Q. T. Le, O. Pedreira, A. Lesniewska, G. Martinez-Alanis, S. Park, Z. Tokei","doi":"10.1109/vlsitechnologyandcir46769.2022.9830150","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830150","url":null,"abstract":"In this paper we demonstrate the functionality of a semi-damascene integration scheme with fully self-aligned vias (FSAV) for interconnects from 26 to 18nm metal pitch (MP), fabricated on 300mm wafers. We have developed a novel integration flow, using the principle of subtractive etching of Ru, on 2 subsequent metal levels. Using structures with programmed overlay shift, we demonstrate the functionality of a fully self-aligned via process which results in working devices with placement errors of up to 5nm. Furthermore, we show via-to-line breakdown field > 9MV/cm, confirming FSAV.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120849522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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