Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346812
J. Pan, P.W. Liu, T. Chang, W. Chiang, C. Tsai, Y. Lin, C. T. Tsai, G. H. Ma, S. Chien, S. Sun
Mobility and strain mechanisms of SiGe channel pMOSFETs fabricated with <110> channel direction on (110) Si substrate (<110>/(110) SiGe channel) have been studied in details for the first time. The combination of substrate orientation, high mobility channel material and extrinsic stained-Si process demonstrates the ultra high mobility enhancement and results in 80% current gain. The piezoresistance coefficients of <110>/(110) SiGe channel p-MOSFETs were also studied to analyze the strain effect on current enhancement. We also compared the derived piezoresistance coefficients results of SiGe channel on (100) and (110) surfaces
{"title":"Mobility and Strain Effects on <110>/(110) SiGe channel pMOSFETs for High Current Enhancement","authors":"J. Pan, P.W. Liu, T. Chang, W. Chiang, C. Tsai, Y. Lin, C. T. Tsai, G. H. Ma, S. Chien, S. Sun","doi":"10.1109/IEDM.2006.346812","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346812","url":null,"abstract":"Mobility and strain mechanisms of SiGe channel pMOSFETs fabricated with <110> channel direction on (110) Si substrate (<110>/(110) SiGe channel) have been studied in details for the first time. The combination of substrate orientation, high mobility channel material and extrinsic stained-Si process demonstrates the ultra high mobility enhancement and results in 80% current gain. The piezoresistance coefficients of <110>/(110) SiGe channel p-MOSFETs were also studied to analyze the strain effect on current enhancement. We also compared the derived piezoresistance coefficients results of SiGe channel on (100) and (110) surfaces","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128384189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346916
T. Yamaguchi, K. Kashihara, T. Okudaira, T. Tsutsumi, K. Maekawa, T. Kosugi, N. Murata, J. Tsuchimoto, K. Shiga, K. Asai, M. Yoneda
It is reported for the first time that the anomalous gate edge leakage current in NMOSFETs is caused by the lateral growth of Ni silicide toward the channel region, and this lateral growth is successfully suppressed by the control of the Ni silicidation region using the Si ion implantation (Si I.I.) technique. As a result, the anomalous gate edge leakage current is successfully reduced, and the standby current and yield for 65nm-node SRAM are greatly improved. This novel technique has high potential for 45nm and 32nm CMOS technology
{"title":"Suppression of Anomalous Gate Edge Leakage Current by Control of Ni Silicidation Region using Si Ion Implantation Technique","authors":"T. Yamaguchi, K. Kashihara, T. Okudaira, T. Tsutsumi, K. Maekawa, T. Kosugi, N. Murata, J. Tsuchimoto, K. Shiga, K. Asai, M. Yoneda","doi":"10.1109/IEDM.2006.346916","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346916","url":null,"abstract":"It is reported for the first time that the anomalous gate edge leakage current in NMOSFETs is caused by the lateral growth of Ni silicide toward the channel region, and this lateral growth is successfully suppressed by the control of the Ni silicidation region using the Si ion implantation (Si I.I.) technique. As a result, the anomalous gate edge leakage current is successfully reduced, and the standby current and yield for 65nm-node SRAM are greatly improved. This novel technique has high potential for 45nm and 32nm CMOS technology","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124757964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346850
S. Tehrani
This paper provide an overview of the recent progress and the nature outlook of MRAM technology. Details of the operation, performance and reliability of Freescale's commercial 4Mbit MRAM device will be presented. Operation and reliability results demonstrating the extension of toggle MRAM to meet industrial and automotive requirements are presented, and new research results on higher-performance materials and advanced scaling approaches are discussed
{"title":"Status and Outlook of MRAM Memory Technology (Invited)","authors":"S. Tehrani","doi":"10.1109/IEDM.2006.346850","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346850","url":null,"abstract":"This paper provide an overview of the recent progress and the nature outlook of MRAM technology. Details of the operation, performance and reliability of Freescale's commercial 4Mbit MRAM device will be presented. Operation and reliability results demonstrating the extension of toggle MRAM to meet industrial and automotive requirements are presented, and new research results on higher-performance materials and advanced scaling approaches are discussed","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123883232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346769
C. J. Kim, Donghun Kang, I. Song, J. Park, Hyuck Lim, Sunil Kim, Eunha Lee, Ranju Chung, Jae Cheol Lee, Young-soo Park
We, for the first time, have successfully fabricated amorphous Ga 2O3-In2O3-ZnO thin film transistor (TFT) with excellent electrical properties and good stability under constant current stress. This transistor shows a field effect mobility of 10 cm2/Vs, an off current below 2 pA and a drain current on-to-off ratio of above 108. The threshold voltage shift was less than 0.2 V for 100 hours at 3 muA and 60 degC. Such stable oxide transistors can be utilized as driving transistor for large area OLED display
{"title":"Highly Stable Ga2O3-In2O3-ZnO TFT for Active-Matrix Organic Light-Emitting Diode Display Application","authors":"C. J. Kim, Donghun Kang, I. Song, J. Park, Hyuck Lim, Sunil Kim, Eunha Lee, Ranju Chung, Jae Cheol Lee, Young-soo Park","doi":"10.1109/IEDM.2006.346769","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346769","url":null,"abstract":"We, for the first time, have successfully fabricated amorphous Ga <sub>2</sub>O<sub>3</sub>-In<sub>2</sub>O<sub>3</sub>-ZnO thin film transistor (TFT) with excellent electrical properties and good stability under constant current stress. This transistor shows a field effect mobility of 10 cm<sup>2</sup>/Vs, an off current below 2 pA and a drain current on-to-off ratio of above 10<sup>8</sup>. The threshold voltage shift was less than 0.2 V for 100 hours at 3 muA and 60 degC. Such stable oxide transistors can be utilized as driving transistor for large area OLED display","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121344740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346968
E. Cole
The explosion in complexity of modern ICs resulting from reduced feature sizes, circuit density, and sophisticated electrical stimulus has made failure analysis and defect localization extremely difficult. Dense metallization and flip-chip packaging can leave only the backside of the IC available for interrogation. Laser-based methods provide some of the powerful tools analysts depend on to overcome these obstacles
{"title":"Laser-Based Defect Localization on Integrated Circuits","authors":"E. Cole","doi":"10.1109/IEDM.2006.346968","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346968","url":null,"abstract":"The explosion in complexity of modern ICs resulting from reduced feature sizes, circuit density, and sophisticated electrical stimulus has made failure analysis and defect localization extremely difficult. Dense metallization and flip-chip packaging can leave only the backside of the IC available for interrogation. Laser-based methods provide some of the powerful tools analysts depend on to overcome these obstacles","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125738965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346864
R. Singanamalla, C. Ravit, G. Vellianitis, J. Pétry, V. Paraschiv, J. van Zijl, S. Brus, M. Verheijen, R. Weemaes, M. Kaiser, J. van Berkum, P. Bancken, R. Vos, H. Yu, K. De Meyer, S. Kubicek, S. Biesemans, J. Hooker
We report band-edge pFET threshold voltage (Vt ~ 0.28 V) for MoOxNy on HfSiON gate dielectric using a standard high temperature gate first metal-inserted poly-stack (MIPS) process flow. We also report p-FETs Vt of 0.45 V using a MoO x/SiON gate stack, meeting the requirement for 45nm high-V t CMOS technology. 30 % improvement in performance compared to our base-line poly-Si/SiON was observed by using both MoOx/SiON and MoOx/HfSiON gate stacks. Excellent dielectric integrity is also shown for devices with MoOxNy gated stack such as device mobility, NBTI and TDDB characteristics, as compared to our base-line poly/SiON devices
我们使用标准的高温栅第一金属插入多晶硅(MIPS)工艺流程报道了HfSiON栅极电介质上MoOxNy的带边pet阈值电压(Vt ~ 0.28 V)。我们还报道了使用MoO x/SiON栅极堆栈的p- fet Vt为0.45 V，满足45nm高Vt CMOS技术的要求。通过使用MoOx/SiON和MoOx/HfSiON栅极堆栈，与我们的基线多晶硅/SiON相比，性能提高了30%。与我们的基线poly/SiON器件相比，具有MoOxNy门控堆栈的器件也显示出优异的介质完整性，例如器件迁移率，NBTI和TDDB特性
{"title":"Low VT Mo(O,N) metal gate electrodes on HfSiON for sub-45nm pMOSFET Devices","authors":"R. Singanamalla, C. Ravit, G. Vellianitis, J. Pétry, V. Paraschiv, J. van Zijl, S. Brus, M. Verheijen, R. Weemaes, M. Kaiser, J. van Berkum, P. Bancken, R. Vos, H. Yu, K. De Meyer, S. Kubicek, S. Biesemans, J. Hooker","doi":"10.1109/IEDM.2006.346864","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346864","url":null,"abstract":"We report band-edge pFET threshold voltage (V<sub>t</sub> ~ 0.28 V) for MoO<sub>x</sub>N<sub>y</sub> on HfSiON gate dielectric using a standard high temperature gate first metal-inserted poly-stack (MIPS) process flow. We also report p-FETs V<sub>t</sub> of 0.45 V using a MoO <sub>x</sub>/SiON gate stack, meeting the requirement for 45nm high-V <sub>t</sub> CMOS technology. 30 % improvement in performance compared to our base-line poly-Si/SiON was observed by using both MoO<sub>x</sub>/SiON and MoO<sub>x</sub>/HfSiON gate stacks. Excellent dielectric integrity is also shown for devices with MoO<sub>x</sub>N<sub>y</sub> gated stack such as device mobility, NBTI and TDDB characteristics, as compared to our base-line poly/SiON devices","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130172540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346778
A. Krishnan, V. Reddy, D. Aldrich, J. Raval, K. Christensen, J. Rosal, C. O'Brien, R. Khamankar, A. Marshall, W. Loh, R. Mckee, S. Krishnan
The SRAM cell sensitivity to transistor degradation is understood using a novel test methodology. A new, semi-empirical model that captures the observed trends is derived. The key findings include (a) cell sensitivity to NBTI degradation is high when low NMOS VT/ high PMOS VT combination arises (b) NBTI contribution to product VMIN drift arises mainly from the mean VTP shift which moves the overall distribution, and (c) NBTI-induced variance is overwhelmed by the time-zero variation of the six transistors of the SRAM. These findings enable a quantitative prediction that the NBTI-induced VMIN increase during burn-in is of the order of the NBTI-induced VT shift
{"title":"SRAM Cell Static Noise Margin and VMIN Sensitivity to Transistor Degradation","authors":"A. Krishnan, V. Reddy, D. Aldrich, J. Raval, K. Christensen, J. Rosal, C. O'Brien, R. Khamankar, A. Marshall, W. Loh, R. Mckee, S. Krishnan","doi":"10.1109/IEDM.2006.346778","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346778","url":null,"abstract":"The SRAM cell sensitivity to transistor degradation is understood using a novel test methodology. A new, semi-empirical model that captures the observed trends is derived. The key findings include (a) cell sensitivity to NBTI degradation is high when low NMOS VT/ high PMOS VT combination arises (b) NBTI contribution to product VMIN drift arises mainly from the mean VTP shift which moves the overall distribution, and (c) NBTI-induced variance is overwhelmed by the time-zero variation of the six transistors of the SRAM. These findings enable a quantitative prediction that the NBTI-induced VMIN increase during burn-in is of the order of the NBTI-induced VT shift","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130287626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346948
Y. Q. Wang, D. Gao, W. Hwang, C. Shen, Gang Zhang, G. Samudra, Y. Yeo, W. Yoo
A Si3N4/SiO2 double-tunneling layer is incorporated in a MONOS memory device structure with high-k HfO 2 charge storage layer for NAND-type memory application. Fast erasure of charges trapped in the high-k layer is enabled by enhanced hole current, accomplishing a large memory window of 2.9 V with electrical stress at 17.5 V for 100 (as and at -18 V for 5 ms. Incorporation of 1.6-1.8 nm thick Si3N4 in place of a part of the SiO2 tunneling layer resulted in fast program and erase (P/E) speed and small Vth shift over 104 endurance cycles
{"title":"Fast erasing and highly reliable MONOS type memory with HfO2 high-k trapping layer and Si3N4/SiO2 tunneling stack","authors":"Y. Q. Wang, D. Gao, W. Hwang, C. Shen, Gang Zhang, G. Samudra, Y. Yeo, W. Yoo","doi":"10.1109/IEDM.2006.346948","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346948","url":null,"abstract":"A Si<sub>3</sub>N<sub>4</sub>/SiO<sub>2</sub> double-tunneling layer is incorporated in a MONOS memory device structure with high-k HfO <sub>2</sub> charge storage layer for NAND-type memory application. Fast erasure of charges trapped in the high-k layer is enabled by enhanced hole current, accomplishing a large memory window of 2.9 V with electrical stress at 17.5 V for 100 (as and at -18 V for 5 ms. Incorporation of 1.6-1.8 nm thick Si<sub>3</sub>N<sub>4</sub> in place of a part of the SiO<sub>2</sub> tunneling layer resulted in fast program and erase (P/E) speed and small V<sub>th</sub> shift over 104 endurance cycles","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134222446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346773
E. Cartier, B. Linder, V. Narayanan, V. Paruchuri
An electrical measurement technique is introduced which provides direct information on the energy distribution of trapped electrons within SiO2/HfO2 dual layer gate stacks of fully processed high-k/metal gate nFETs. Using this electron spectroscopic technique, it is shown that electron trap levels in HfO2 are located adjacent to the conduction band of Si with trap energies which agree with recently calculated defect levels induced by oxygen vacancy defects in HfO2. A strong sensitivity of these shallow defects to the gate stack processing conditions is observed and it is found that the Positive Bias Temperature Instability (PBTI) can be reduced by suppressing oxygen vacancy formation in the HfO2 layer
{"title":"Fundamental understanding and optimization of PBTI in nFETs with SiO2/HfO2 gate stack","authors":"E. Cartier, B. Linder, V. Narayanan, V. Paruchuri","doi":"10.1109/IEDM.2006.346773","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346773","url":null,"abstract":"An electrical measurement technique is introduced which provides direct information on the energy distribution of trapped electrons within SiO2/HfO2 dual layer gate stacks of fully processed high-k/metal gate nFETs. Using this electron spectroscopic technique, it is shown that electron trap levels in HfO2 are located adjacent to the conduction band of Si with trap energies which agree with recently calculated defect levels induced by oxygen vacancy defects in HfO2. A strong sensitivity of these shallow defects to the gate stack processing conditions is observed and it is found that the Positive Bias Temperature Instability (PBTI) can be reduced by suppressing oxygen vacancy formation in the HfO2 layer","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130952319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346866
B. Ju, S.C. Song, T. Lee, B. Sassman, C. Kang, B. Lee, R. Jammy
A dry etch process for metal/high-k stacks has been developed to solve the integration problems associated with wet etch removal of high-k dielectric from the source and drain (S/D) areas. An in-situ plasma (O2) treatment has been introduced for the first time to cure the damage induced by the high-k dry etch process. Excellent electrical performances, such as dramatically improved leakage current, superior Ion/Ioff performance, and suppressed short channel effects (gate induced drain leakage, drain-induced barrier lowering, Vt distribution) are achieved. With this novel process, metal/high-k gate stack dry etch process for very short channel devices becomes more manufacturing worthy, which has been one of the critical integration challenges in realizing gate first CMOSFETs with metal/high-k
{"title":"A novel in situ plasma treatment for damage-free metal/high-k gate stack RIE process","authors":"B. Ju, S.C. Song, T. Lee, B. Sassman, C. Kang, B. Lee, R. Jammy","doi":"10.1109/IEDM.2006.346866","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346866","url":null,"abstract":"A dry etch process for metal/high-k stacks has been developed to solve the integration problems associated with wet etch removal of high-k dielectric from the source and drain (S/D) areas. An in-situ plasma (O2) treatment has been introduced for the first time to cure the damage induced by the high-k dry etch process. Excellent electrical performances, such as dramatically improved leakage current, superior Ion/Ioff performance, and suppressed short channel effects (gate induced drain leakage, drain-induced barrier lowering, Vt distribution) are achieved. With this novel process, metal/high-k gate stack dry etch process for very short channel devices becomes more manufacturing worthy, which has been one of the critical integration challenges in realizing gate first CMOSFETs with metal/high-k","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132942820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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