Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346823
A. Arreghini, F. Driussi, D. Esseni, L. Selmi, M. van Duuren, R. van Schaijk
In this work, we report experiments on SONOS memory cells aimed to investigate the vertical position and the nature of the charge trapped in the gate stack during program/erase (P/E) cycling. To this purpose a new experimental setup has been developed to accurately detect the amount of injected charge and the consequent threshold voltage shift. The results, confirmed by different measurement techniques, show that the position of the charge centroid during program and erase operation is quite insensitive to the injection conditions. Moreover, we investigate by means of carrier separation experiments the role of the different type of carriers during program and erase operation of SONOS cells
{"title":"Experimental Extraction of the Charge Centroid and of the Charge Type in the P/E Operation of Sonos Memory Cells","authors":"A. Arreghini, F. Driussi, D. Esseni, L. Selmi, M. van Duuren, R. van Schaijk","doi":"10.1109/IEDM.2006.346823","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346823","url":null,"abstract":"In this work, we report experiments on SONOS memory cells aimed to investigate the vertical position and the nature of the charge trapped in the gate stack during program/erase (P/E) cycling. To this purpose a new experimental setup has been developed to accurately detect the amount of injected charge and the consequent threshold voltage shift. The results, confirmed by different measurement techniques, show that the position of the charge centroid during program and erase operation is quite insensitive to the injection conditions. Moreover, we investigate by means of carrier separation experiments the role of the different type of carriers during program and erase operation of SONOS cells","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132097929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346729
B. Cho, Takahiro Yasue, H. Yoon, Moon-sook Lee, I. Yeo, U. Chung, J. Moon, B. Ryu
The feasibility of the charge-transfer based polymer resistive memory as a future data storage device was tested using a thermally robust polyimide and PCBM composite film, available by low-cost solution processing. The prototype device with a simple 4F cross-point cell structure demonstrated basic non-volatile memory functions (> 1000 write/erase cycles and 1-week data retention in an ambient without encapsulation). Not only bi-polar but also uni-polar operation scheme with multi-level programming worked for the device. The cells on both the top and the bottom layers of a stacked device with additional heat budget of > 300 degC for 1 hour exhibited no degradation on the performance
{"title":"Thermally Robust Multi-layer Non-Volatile Polymer Resistive Memory","authors":"B. Cho, Takahiro Yasue, H. Yoon, Moon-sook Lee, I. Yeo, U. Chung, J. Moon, B. Ryu","doi":"10.1109/IEDM.2006.346729","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346729","url":null,"abstract":"The feasibility of the charge-transfer based polymer resistive memory as a future data storage device was tested using a thermally robust polyimide and PCBM composite film, available by low-cost solution processing. The prototype device with a simple 4F cross-point cell structure demonstrated basic non-volatile memory functions (> 1000 write/erase cycles and 1-week data retention in an ambient without encapsulation). Not only bi-polar but also uni-polar operation scheme with multi-level programming worked for the device. The cells on both the top and the bottom layers of a stacked device with additional heat budget of > 300 degC for 1 hour exhibited no degradation on the performance","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"193 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115630222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346906
D. Mantegazza, D. Ielmini, A. Pirovano, B. Gleixner, A. Lacaita, E. Varesi, F. Pellizzer, R. Bez
In order to integrate phase change memory (PCM) devices into large and yielding arrays, a programming window between the two memory logic states must exist with a probability of error less than 10-9 (1 PPB). Understanding and removing the mechanisms of cell failure during the programming operation is therefore required for this technology to be viable. This paper discusses new methodologies for PCM failure electrical characterization, discovers two potential failure mechanisms and proposes new approaches for improvements
{"title":"Electrical characterization of anomalous cells in phase change memory arrays","authors":"D. Mantegazza, D. Ielmini, A. Pirovano, B. Gleixner, A. Lacaita, E. Varesi, F. Pellizzer, R. Bez","doi":"10.1109/IEDM.2006.346906","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346906","url":null,"abstract":"In order to integrate phase change memory (PCM) devices into large and yielding arrays, a programming window between the two memory logic states must exist with a probability of error less than 10-9 (1 PPB). Understanding and removing the mechanisms of cell failure during the programming operation is therefore required for this technology to be viable. This paper discusses new methodologies for PCM failure electrical characterization, discovers two potential failure mechanisms and proposes new approaches for improvements","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114776069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346974
H. Sumi
Image sensors are widely used in the high-volume markets of digital still cameras and camcorders. In recent years, mobile phones with cameras have employed CMOS image sensors because of their low power consumption and single power supply. Initially, CMOS image sensors were inexpensive and provided poor imaging performance. However, more recently, some CMOS image sensors have achieved high-quality imaging performance comparable to that of the CCD. The present paper reviews the challenges of image sensor development over the last few decades and discusses the technology and design architecture for low-noise mega-pixel CMOS image sensors
{"title":"Low-noise Imaging System with CMOS Sensor for High-Quality Imaging","authors":"H. Sumi","doi":"10.1109/IEDM.2006.346974","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346974","url":null,"abstract":"Image sensors are widely used in the high-volume markets of digital still cameras and camcorders. In recent years, mobile phones with cameras have employed CMOS image sensors because of their low power consumption and single power supply. Initially, CMOS image sensors were inexpensive and provided poor imaging performance. However, more recently, some CMOS image sensors have achieved high-quality imaging performance comparable to that of the CCD. The present paper reviews the challenges of image sensor development over the last few decades and discusses the technology and design architecture for low-noise mega-pixel CMOS image sensors","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114382105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.347001
J. Scholvin, David R. Greenberg, Jesus A. del Alamo
This study compares the RF power performance of 65 nm and 0.25 mum CMOS devices integrated on an advanced 65 nm process, and discusses their power and frequency limitations for the first time. The authors demonstrate output power levels of about 80 mW for 65 nm devices, and 450 mW for 0.25 mum devices when operated at their nominal voltages of 1.0 and 2.5 V respectively. The authors find that output power as well as the maximum frequency is limited by parasitic resistances in the backend. The results provide insight into the performance potential of RF power amplifiers integrated into advanced CMOS technologies in SoC applications
{"title":"Fundamental Power and Frequency Limits of Deeply-Scaled CMOS for RF Power Applications","authors":"J. Scholvin, David R. Greenberg, Jesus A. del Alamo","doi":"10.1109/IEDM.2006.347001","DOIUrl":"https://doi.org/10.1109/IEDM.2006.347001","url":null,"abstract":"This study compares the RF power performance of 65 nm and 0.25 mum CMOS devices integrated on an advanced 65 nm process, and discusses their power and frequency limitations for the first time. The authors demonstrate output power levels of about 80 mW for 65 nm devices, and 450 mW for 0.25 mum devices when operated at their nominal voltages of 1.0 and 2.5 V respectively. The authors find that output power as well as the maximum frequency is limited by parasitic resistances in the backend. The results provide insight into the performance potential of RF power amplifiers integrated into advanced CMOS technologies in SoC applications","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114708583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.347003
Chen Yang, T. Ren, Feng Liu, Li-tian Liu, Guang Chen, X. Guan, A. Wang
This paper reports fabrication of on-chip RF integrated inductors with spin-coated ferrite thin-films (Ni-Zn-Cu-Fe-O, Y-Bi-Fe-O and Co-Zr-O) and high-frequency characterization using equivalent circuit model. Measurement results show that, compared with air-cored inductor, the inductance (L) of Y-Bi-Fe-O and Co-Zr-O thin-film samples increases by 26-50% and 20-39% in 0.1-9GHz, respectively; while the quality factor (Q) of Co-Zr-O inductor is improved by 25-59%. This work demonstrates that the ferrite thin-films are promising for making high-performance integrated compact inductors for RF IC applications
{"title":"On-Chip Integrated Inductors with Ferrite Thin-films for RF IC","authors":"Chen Yang, T. Ren, Feng Liu, Li-tian Liu, Guang Chen, X. Guan, A. Wang","doi":"10.1109/IEDM.2006.347003","DOIUrl":"https://doi.org/10.1109/IEDM.2006.347003","url":null,"abstract":"This paper reports fabrication of on-chip RF integrated inductors with spin-coated ferrite thin-films (Ni-Zn-Cu-Fe-O, Y-Bi-Fe-O and Co-Zr-O) and high-frequency characterization using equivalent circuit model. Measurement results show that, compared with air-cored inductor, the inductance (L) of Y-Bi-Fe-O and Co-Zr-O thin-film samples increases by 26-50% and 20-39% in 0.1-9GHz, respectively; while the quality factor (Q) of Co-Zr-O inductor is improved by 25-59%. This work demonstrates that the ferrite thin-films are promising for making high-performance integrated compact inductors for RF IC applications","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117243290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346883
M. Ball, J. Rosal, R. Mckee, W. Loh, T. Houston, R. Garcia, J. Raval, D. Li, R. Hollingsworth, R. Gury, R. Eklund, J. Vaccani, B. Castellano, F. Piacibello, S. Ashburn, A. Tsao, A. Krishnan, J. Ondrusek, T. Anderson
SRAMs are an integral part of system on chip devices. With transistor and gate length scaling to 65nm/45nm nodes, SRAM stability across the product's lifetime has become a challenge. Negative bias temperature instability, defects, or other phenomena that may manifest itself as a transistor threshold voltage (VT) increase can result in VMIN drift of SRAM memory cells through burn-in and/or operation. A direct assessment at time-zero is difficult because the transistor VT has not yet shifted, and therefore no capability to screen VMIN shift at time zero can be developed. This work describes a methodology developed on 65nm low power and high performance process technologies at Texas Instruments for screening SRAM cells at time zero before they become reliability issues
{"title":"A Screening Methodology for VMIN Drift in SRAM Arrays with Application to Sub-65nm Nodes","authors":"M. Ball, J. Rosal, R. Mckee, W. Loh, T. Houston, R. Garcia, J. Raval, D. Li, R. Hollingsworth, R. Gury, R. Eklund, J. Vaccani, B. Castellano, F. Piacibello, S. Ashburn, A. Tsao, A. Krishnan, J. Ondrusek, T. Anderson","doi":"10.1109/IEDM.2006.346883","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346883","url":null,"abstract":"SRAMs are an integral part of system on chip devices. With transistor and gate length scaling to 65nm/45nm nodes, SRAM stability across the product's lifetime has become a challenge. Negative bias temperature instability, defects, or other phenomena that may manifest itself as a transistor threshold voltage (VT) increase can result in VMIN drift of SRAM memory cells through burn-in and/or operation. A direct assessment at time-zero is difficult because the transistor VT has not yet shifted, and therefore no capability to screen VMIN shift at time zero can be developed. This work describes a methodology developed on 65nm low power and high performance process technologies at Texas Instruments for screening SRAM cells at time zero before they become reliability issues","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116177901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346821
N. Tega, Hiroshi Miki, T. Osabe, A. Kotabe, K. Otsuga, Hideaki Kurata, Shiro Kamohara, Kenji Tokami, Yoshihiro Ikeda, Renichi Yamada
A threshold voltage fluctuation (DeltaVth) due to random telegraph signal (RTS) in a floating-gate (FG) flash memory was investigated. From statistical analysis of the DeltaVth, we found an anomalously large DeltaVth at high percentage region of the DeltaVth distribution, which is caused by a complex RTS. Since the ratio of the complex RTS among the RTS is increased by charge injection to tunnel oxide, the dispersion of the DeltaVth distribution increases after program/erase (P/E) cycle. Since the DeltaVth due to the complex RTS is much larger than the simple RTS, the complex RTS become one of the reliability issues in larger capacity flash memory, especially after P/E cycle
{"title":"Anomalously Large Threshold Voltage Fluctuation by Complex Random Telegraph Signal in Floating Gate Flash Memory","authors":"N. Tega, Hiroshi Miki, T. Osabe, A. Kotabe, K. Otsuga, Hideaki Kurata, Shiro Kamohara, Kenji Tokami, Yoshihiro Ikeda, Renichi Yamada","doi":"10.1109/IEDM.2006.346821","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346821","url":null,"abstract":"A threshold voltage fluctuation (DeltaVth) due to random telegraph signal (RTS) in a floating-gate (FG) flash memory was investigated. From statistical analysis of the DeltaVth, we found an anomalously large DeltaVth at high percentage region of the DeltaVth distribution, which is caused by a complex RTS. Since the ratio of the complex RTS among the RTS is increased by charge injection to tunnel oxide, the dispersion of the DeltaVth distribution increases after program/erase (P/E) cycle. Since the DeltaVth due to the complex RTS is much larger than the simple RTS, the complex RTS become one of the reliability issues in larger capacity flash memory, especially after P/E cycle","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"35 11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116243592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346893
P. Nicollian, A. Krishnan, C. Chancellor, R. Khamankar
The paper shows that a minimum of two traps is required to cause breakdown in SiON films down to 10A. At least one trap must be an interface state and at least one must be a bulk state. At low voltages, the rate limiting step for breakdown is the generation of interface traps and is controlled by the release of H0
{"title":"The Traps that cause Breakdown in Deeply Scaled SiON Dielectrics","authors":"P. Nicollian, A. Krishnan, C. Chancellor, R. Khamankar","doi":"10.1109/IEDM.2006.346893","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346893","url":null,"abstract":"The paper shows that a minimum of two traps is required to cause breakdown in SiON films down to 10A. At least one trap must be an interface state and at least one must be a bulk state. At low voltages, the rate limiting step for breakdown is the generation of interface traps and is controlled by the release of H0","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123413991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346898
Y. Wang, V. Lee, K. Cheung
Frequency dependent charge pumping measurement has become an important tool for high-k dielectric reliability investigation. The interpretation of how deep the technique probes has become a controversy with important implication on the reliability of the high-k gate dielectric. The paper examines this problem experimentally and theoretically in this paper. Charge pumping experiment has been carried out to beyond 1GHz for the first time, providing evidence that neither of the existing models is correct. The paper proposes a new theoretical model that is consistent with the new data
{"title":"Frequency Dependent Charge-Pumping, How deep does it probe?","authors":"Y. Wang, V. Lee, K. Cheung","doi":"10.1109/IEDM.2006.346898","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346898","url":null,"abstract":"Frequency dependent charge pumping measurement has become an important tool for high-k dielectric reliability investigation. The interpretation of how deep the technique probes has become a controversy with important implication on the reliability of the high-k gate dielectric. The paper examines this problem experimentally and theoretically in this paper. Charge pumping experiment has been carried out to beyond 1GHz for the first time, providing evidence that neither of the existing models is correct. The paper proposes a new theoretical model that is consistent with the new data","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123919151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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