Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820955
Shiho Kim, Il-Suk Yang, Won-Jae Lee, I. You, B. Yu, K. Cho
A nonvolatile single transistor type FRAM is proposed. To overcome the selection problem of one-transistor-type FRAM, each well is isolated from adjacent columns, hence, the well bias can be controlled individually and can be floating state. The results of HSPICE simulations showed the successful operations of the proposed cell array. The worst gate disturb voltage of unselected cell is less than 2 V, which satisfies V/3 rule.
{"title":"A single transistor ferroelectric RAM with nondestructive readout operations","authors":"Shiho Kim, Il-Suk Yang, Won-Jae Lee, I. You, B. Yu, K. Cho","doi":"10.1109/ICVC.1999.820955","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820955","url":null,"abstract":"A nonvolatile single transistor type FRAM is proposed. To overcome the selection problem of one-transistor-type FRAM, each well is isolated from adjacent columns, hence, the well bias can be controlled individually and can be floating state. The results of HSPICE simulations showed the successful operations of the proposed cell array. The worst gate disturb voltage of unselected cell is less than 2 V, which satisfies V/3 rule.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"218 1","pages":"433-436"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76066960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820873
Seonghearn Lee, Hyun-Kyu Yu
We investigate non-physical phenomena occurring in extracting MOSFET parameters of a conventional small-signal model in detail. In order to eliminate these phenomena, an improved small-signal model connecting the drain-bulk junction capacitance into the external source has been developed. This improved model allows us to extract frequency-independent parameters in the wide range of frequency while maintaining the physical validity. Good agreement between measured and modeled gain plots is achieved in the frequency range of 0.5 to 39.5 GHz.
{"title":"Improved small-signal modeling of RF Si MOSFETs","authors":"Seonghearn Lee, Hyun-Kyu Yu","doi":"10.1109/ICVC.1999.820873","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820873","url":null,"abstract":"We investigate non-physical phenomena occurring in extracting MOSFET parameters of a conventional small-signal model in detail. In order to eliminate these phenomena, an improved small-signal model connecting the drain-bulk junction capacitance into the external source has been developed. This improved model allows us to extract frequency-independent parameters in the wide range of frequency while maintaining the physical validity. Good agreement between measured and modeled gain plots is achieved in the frequency range of 0.5 to 39.5 GHz.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"31 1","pages":"197-200"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79002869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820974
Jongwan Jung, Byung-Sung Song, Ki-Wuk Nam, Sang-Wuk Ha, Dae-Byung Kim
For the first time it is shown that charging damage during RF power turn-off is as severe as steady state charging in both MERIE and ICP system. A newly proposed 2-step power down method dramatically reduced the charging damage during rf power turn-off. Moreover this method has shown highly reproducible results.
{"title":"Dramatic reduction of plasma induced damage using 2-step power down method in metal etch process","authors":"Jongwan Jung, Byung-Sung Song, Ki-Wuk Nam, Sang-Wuk Ha, Dae-Byung Kim","doi":"10.1109/ICVC.1999.820974","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820974","url":null,"abstract":"For the first time it is shown that charging damage during RF power turn-off is as severe as steady state charging in both MERIE and ICP system. A newly proposed 2-step power down method dramatically reduced the charging damage during rf power turn-off. Moreover this method has shown highly reproducible results.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"43 1","pages":"476-479"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82535040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820850
Seung Woo Lee, S. Jeon, Jong Chun Park, Jong-Hyon Ahn, Y. W. Kim, K. Suh
A highly manufacturable and high performance 0.13 /spl mu/m CMOS process for a 1.5 V microprocessor is proposed. The device is integrated by dual-doped poly-Si transistors with STI, additionally doped gate poly, highly doped drain extension and Co-salicide structure. Co-salicide gate with sheet resistance below 5 ohm/sq. in the 0.1 /spl mu/m -length gate line is obtained. By using indium and boron as channel implants, and employing n/sup +/poly gates for nMOS while low-energy boron instead of BF2 is used for pMOS gates, the Idsat values of 770 /spl mu/A//spl mu/m and 31 /spl mu/A//spl mu/m have been achieved with the electrical gate oxide thickness of 2.6 nm and 2.8 nm for nMOS and pMOS, respectively.
{"title":"A high performance 0.13 /spl mu/m CMOS process for GHz microprocessor manufacture","authors":"Seung Woo Lee, S. Jeon, Jong Chun Park, Jong-Hyon Ahn, Y. W. Kim, K. Suh","doi":"10.1109/ICVC.1999.820850","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820850","url":null,"abstract":"A highly manufacturable and high performance 0.13 /spl mu/m CMOS process for a 1.5 V microprocessor is proposed. The device is integrated by dual-doped poly-Si transistors with STI, additionally doped gate poly, highly doped drain extension and Co-salicide structure. Co-salicide gate with sheet resistance below 5 ohm/sq. in the 0.1 /spl mu/m -length gate line is obtained. By using indium and boron as channel implants, and employing n/sup +/poly gates for nMOS while low-energy boron instead of BF2 is used for pMOS gates, the Idsat values of 770 /spl mu/A//spl mu/m and 31 /spl mu/A//spl mu/m have been achieved with the electrical gate oxide thickness of 2.6 nm and 2.8 nm for nMOS and pMOS, respectively.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"22 1","pages":"136-139"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85018236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820910
Je-Hyuk Ryu, Sang Cheon Kim, Jun-Dong Cho, Hyun Woo Park, Yung Hoon Chang
This paper presents a new algorithm on lower-power survivor path memory implementation of the trace-back systolic array Viterbi algorithm. A novel idea is to reuse the already-generated trace-back routes to reduce the number of trace-back operations. It results in increasing the area of spurious switching activity region, and further reducing the switching activity with gated-clocks during trace-back operation. With the SYNOPSYS power estimation tool, DesignPower, our experimental result shows on the average 40% reduction in power with the same latency at a cost of 23% increase in area against the trace-back unit introduced by Truong et al. (1992). The proposed survivor memory scheme can be applied to the digital communication systems for targeting low power consumption.
{"title":"Lower power Viterbi decoder architecture with a new clock-gating trace-back unit","authors":"Je-Hyuk Ryu, Sang Cheon Kim, Jun-Dong Cho, Hyun Woo Park, Yung Hoon Chang","doi":"10.1109/ICVC.1999.820910","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820910","url":null,"abstract":"This paper presents a new algorithm on lower-power survivor path memory implementation of the trace-back systolic array Viterbi algorithm. A novel idea is to reuse the already-generated trace-back routes to reduce the number of trace-back operations. It results in increasing the area of spurious switching activity region, and further reducing the switching activity with gated-clocks during trace-back operation. With the SYNOPSYS power estimation tool, DesignPower, our experimental result shows on the average 40% reduction in power with the same latency at a cost of 23% increase in area against the trace-back unit introduced by Truong et al. (1992). The proposed survivor memory scheme can be applied to the digital communication systems for targeting low power consumption.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"32 1","pages":"297-300"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86130521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820905
B. Jeon, Moon-Kyu Choi, Seung-Gyu Oh, Yeonbae Chung, K. Suh, Kinam Kim
This paper proposes a novel method to evaluate the real cell ferroelectric capacitor with 4 Mb nonvolatile ferroelectric RAM which has a Cell Charge Evaluation Scheme (CCES). The charge value and the distribution of the memory cell ferroelectric capacitor can be evaluated by the CCES. Additionally, it can easily screen out weak bits which have smaller charges than normal cells by using the CCES as a bit-line reference voltage generator.
{"title":"A novel cell charge evaluation scheme and test method for 4 Mb nonvolatile ferroelectric RAM","authors":"B. Jeon, Moon-Kyu Choi, Seung-Gyu Oh, Yeonbae Chung, K. Suh, Kinam Kim","doi":"10.1109/ICVC.1999.820905","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820905","url":null,"abstract":"This paper proposes a novel method to evaluate the real cell ferroelectric capacitor with 4 Mb nonvolatile ferroelectric RAM which has a Cell Charge Evaluation Scheme (CCES). The charge value and the distribution of the memory cell ferroelectric capacitor can be evaluated by the CCES. Additionally, it can easily screen out weak bits which have smaller charges than normal cells by using the CCES as a bit-line reference voltage generator.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"19 1","pages":"281-284"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75548372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820963
Byoung-Ho Kwon, Jong-Hyup Lee, Hee-Jeen Kim, Seoung Soo Kweon, Young-Gyoon Ryu, Jeong-Gun Lee
The effect of pattern density, trench width and selectivity of slurry on dishing and erosion in STI CMP process was investigated by using specially designed isolation pattern. As trench width gets wider and active pattern density gets higher, dishing becomes more severe. Low selectivity slurry shows less dishing at over 20 /spl mu/m trench width, whereas high selectivity slurry shows less dishing at below 20 /spl mu/m trench. Erosion of low active pattern density area is more severe and it is not affected by trench width. Generally, high selectivity slurry induces less erosion.
{"title":"Dishing and erosion in STI CMP","authors":"Byoung-Ho Kwon, Jong-Hyup Lee, Hee-Jeen Kim, Seoung Soo Kweon, Young-Gyoon Ryu, Jeong-Gun Lee","doi":"10.1109/ICVC.1999.820963","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820963","url":null,"abstract":"The effect of pattern density, trench width and selectivity of slurry on dishing and erosion in STI CMP process was investigated by using specially designed isolation pattern. As trench width gets wider and active pattern density gets higher, dishing becomes more severe. Low selectivity slurry shows less dishing at over 20 /spl mu/m trench width, whereas high selectivity slurry shows less dishing at below 20 /spl mu/m trench. Erosion of low active pattern density area is more severe and it is not affected by trench width. Generally, high selectivity slurry induces less erosion.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"157 1","pages":"456-458"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75843734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820889
Kwangseok Han, Ilgweon Kim, Hyungcheol Shin
The nano-crystal memory operates at low voltage compared to conventional flash memory due to thinner tunneling dielectrics since the spacing between the Si dots suppresses the charge loss through lateral paths. Recently, p-channel nano-crystal memory, which stores holes instead of electrons as the information, has been reported to have good characteristics compared with EEPROM. In this paper, the characteristics of tunneling oxide and tunneling ON is compared for p-channel nano-crystal memory.
{"title":"Comparison of the characteristics of tunneling oxide and tunneling ON for p-channel nano-crystal memory","authors":"Kwangseok Han, Ilgweon Kim, Hyungcheol Shin","doi":"10.1109/ICVC.1999.820889","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820889","url":null,"abstract":"The nano-crystal memory operates at low voltage compared to conventional flash memory due to thinner tunneling dielectrics since the spacing between the Si dots suppresses the charge loss through lateral paths. Recently, p-channel nano-crystal memory, which stores holes instead of electrons as the information, has been reported to have good characteristics compared with EEPROM. In this paper, the characteristics of tunneling oxide and tunneling ON is compared for p-channel nano-crystal memory.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"13 1","pages":"233-236"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73095567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820923
O. Kwon, Ki-Nam Park, Do-Young Lee, Kang-Jin Lee, S. Jun, Chan-Ki Kim, W. Yang
In this paper, a novel double slope ADC (Analog-to-Digital Converter) for imaging applications is proposed. With this conversion technique, the resolution of images can be increased especially for low illumination environments while maintaining wide dynamic range. The proposed double slope ADC is implemented with a parallel bank of 640 pseudo-l0b ADCs in a 3.3 V single chip digital CMOS image sensor with 640/spl times/480 (VGA) pixel array, 3.04 kB DRAM line buffer, and digital control block using a 0.5 /spl mu/m single poly, triple metal DRAM baseline.
{"title":"A novel double slope analog-to-digital converter for a high-quality 640/spl times/480 CMOS imaging system","authors":"O. Kwon, Ki-Nam Park, Do-Young Lee, Kang-Jin Lee, S. Jun, Chan-Ki Kim, W. Yang","doi":"10.1109/ICVC.1999.820923","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820923","url":null,"abstract":"In this paper, a novel double slope ADC (Analog-to-Digital Converter) for imaging applications is proposed. With this conversion technique, the resolution of images can be increased especially for low illumination environments while maintaining wide dynamic range. The proposed double slope ADC is implemented with a parallel bank of 640 pseudo-l0b ADCs in a 3.3 V single chip digital CMOS image sensor with 640/spl times/480 (VGA) pixel array, 3.04 kB DRAM line buffer, and digital control block using a 0.5 /spl mu/m single poly, triple metal DRAM baseline.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"29 1","pages":"335-338"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74573185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.821014
Kwanyeob Chae, H. Ki, In-Chul Hwang, S. Kim
A double precharge TSPC D-flip-flop (DFF) is proposed and a 3 GHz dual-modulus prescaler using the double precharge TSPC in 0.35 /spl mu/m CMOS technology is presented in this paper. The double precharge TSPC DFF can reduce setup time compared with the conventional one, so it contributes to enhancing the operating speed of a dual-modulus prescaler. A 128/129 dual-modulus prescaler using the proposed flip-flop shows a maximum operating frequency of 3 GHz with 16 mW power consumption at 3.3 V power supply.
{"title":"Double precharge TSPC for high-speed dual-modulus prescaler","authors":"Kwanyeob Chae, H. Ki, In-Chul Hwang, S. Kim","doi":"10.1109/ICVC.1999.821014","DOIUrl":"https://doi.org/10.1109/ICVC.1999.821014","url":null,"abstract":"A double precharge TSPC D-flip-flop (DFF) is proposed and a 3 GHz dual-modulus prescaler using the double precharge TSPC in 0.35 /spl mu/m CMOS technology is presented in this paper. The double precharge TSPC DFF can reduce setup time compared with the conventional one, so it contributes to enhancing the operating speed of a dual-modulus prescaler. A 128/129 dual-modulus prescaler using the proposed flip-flop shows a maximum operating frequency of 3 GHz with 16 mW power consumption at 3.3 V power supply.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"52 1","pages":"609-612"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73748696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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