Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820825
Joon-Ho Choi, Young-Seok Hong, Chang-Woo Ko, Y. Kim, Taek-Soo Kim, J. Kong
In today's advanced semiconductor products, the width of the bus and the operating frequency increase. As a result, more simultaneous switching noise (SSN) is observed. However, SSN analysis requires the modeling of power and ground planes. The PEEC (Partial Element Equivalent Circuit) method is often used for modeling the planes but it suffers from a large amount of computation time and the limited size of PCB it can handle. This paper proposes a new fast method of generating an equivalent circuit networks for multi-layer packages and PCBs. A library of parasitics is built for different vertical structures and materials by using a electromagnetic field solver. This library is used to generate the equivalent circuit without the need for the complex field solving procedure. Compared to the conventional method (PEEC), the proposed method drastically reduces the time and effort for generating the equivalent circuit model with the same accuracy. This method has been used to design a variety of high speed memory module products.
{"title":"An efficient simultaneous switching noise analysis of high density multi-layer packages and PCBs considering the power and ground planes","authors":"Joon-Ho Choi, Young-Seok Hong, Chang-Woo Ko, Y. Kim, Taek-Soo Kim, J. Kong","doi":"10.1109/ICVC.1999.820825","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820825","url":null,"abstract":"In today's advanced semiconductor products, the width of the bus and the operating frequency increase. As a result, more simultaneous switching noise (SSN) is observed. However, SSN analysis requires the modeling of power and ground planes. The PEEC (Partial Element Equivalent Circuit) method is often used for modeling the planes but it suffers from a large amount of computation time and the limited size of PCB it can handle. This paper proposes a new fast method of generating an equivalent circuit networks for multi-layer packages and PCBs. A library of parasitics is built for different vertical structures and materials by using a electromagnetic field solver. This library is used to generate the equivalent circuit without the need for the complex field solving procedure. Compared to the conventional method (PEEC), the proposed method drastically reduces the time and effort for generating the equivalent circuit model with the same accuracy. This method has been used to design a variety of high speed memory module products.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"56 1","pages":"65-68"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75057298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820848
W. Kim, Jong-Kook Kim, Choong-Bao Kim, C. Choi, Jin-Woong Kim, Yil-Wook Kim, I. Choi
To obtain a top corner rounding in the Shallow Trench Isolation (STI) process with a hard mask, a new etching spacer and Si soft etching for an useful top corner process is evaluated. This technique utilizes the oxide rounding and, thus, effectively suppresses the inverse narrow width effect due to the stress reduction at the top corner and the less interface influence between active and field oxide. Also this technique showed no degradation of junction leakage current and less profile micro-loading effect compared with the conventional resist mask process. As a result, it has been found that this technique is very effective for sub-0.15 /spl mu/m STI formation.
{"title":"New corner rounding process for sub-0.15 /spl mu/m shallow trench isolation","authors":"W. Kim, Jong-Kook Kim, Choong-Bao Kim, C. Choi, Jin-Woong Kim, Yil-Wook Kim, I. Choi","doi":"10.1109/ICVC.1999.820848","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820848","url":null,"abstract":"To obtain a top corner rounding in the Shallow Trench Isolation (STI) process with a hard mask, a new etching spacer and Si soft etching for an useful top corner process is evaluated. This technique utilizes the oxide rounding and, thus, effectively suppresses the inverse narrow width effect due to the stress reduction at the top corner and the less interface influence between active and field oxide. Also this technique showed no degradation of junction leakage current and less profile micro-loading effect compared with the conventional resist mask process. As a result, it has been found that this technique is very effective for sub-0.15 /spl mu/m STI formation.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"279 1","pages":"133-135"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76294761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.821004
Jin-Cheon Kim, Sanghoon Lee, Hong-June Park
A half-swing clocking scheme with a complementary gate and source drive was proposed for CMOS flip-flop to reduce the power consumption of the clock system by 43%, while keeping the flip-flop delay time to be the same as that of the conventional full-swing clocking scheme. The delay time of the preceding half stage of flip-flop using this scheme is less than half that using the previous half-swing clocking scheme.
{"title":"A high-speed 50% power-saving half-swing clocking scheme for flip-flop with complementary gate and source drive","authors":"Jin-Cheon Kim, Sanghoon Lee, Hong-June Park","doi":"10.1109/ICVC.1999.821004","DOIUrl":"https://doi.org/10.1109/ICVC.1999.821004","url":null,"abstract":"A half-swing clocking scheme with a complementary gate and source drive was proposed for CMOS flip-flop to reduce the power consumption of the clock system by 43%, while keeping the flip-flop delay time to be the same as that of the conventional full-swing clocking scheme. The delay time of the preceding half stage of flip-flop using this scheme is less than half that using the previous half-swing clocking scheme.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"174 1","pages":"574-577"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75984213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820859
S. Bae, Do-Hwa Lee, Hee-Mok Lee, Myung-Goon Gill, B. Kim, D. Ahn
We discuss a duplicate repairing process for opaque repair by means of a Ga/sup +/ focussed ion beam (FIB) and a blue laser scanning on a MoSiON phase shift mask. We show the pattern fidelity and edge roughness on the wafer and photomask substrates. The aerial images and intensity profiles produced by the AIMS tool show the fine resolution capability. Although somewhat resolved, we must consider the specifications of CD control for next generation devices such as design rules of 0.15 /spl mu/m. We evaluate the printability of the half-tone phase shift mask with i-line and KrF steppers after defect repair. We also confirm the accuracy of edge repair, Ga+ deep implantation effects and the environmental stability of FIB and blue laser repair tools. Finally, we measure the topography of the repaired photomask by AFM and AIMS.
{"title":"Investigation of half-tone phase shift mask with FIB and blue laser repair","authors":"S. Bae, Do-Hwa Lee, Hee-Mok Lee, Myung-Goon Gill, B. Kim, D. Ahn","doi":"10.1109/ICVC.1999.820859","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820859","url":null,"abstract":"We discuss a duplicate repairing process for opaque repair by means of a Ga/sup +/ focussed ion beam (FIB) and a blue laser scanning on a MoSiON phase shift mask. We show the pattern fidelity and edge roughness on the wafer and photomask substrates. The aerial images and intensity profiles produced by the AIMS tool show the fine resolution capability. Although somewhat resolved, we must consider the specifications of CD control for next generation devices such as design rules of 0.15 /spl mu/m. We evaluate the printability of the half-tone phase shift mask with i-line and KrF steppers after defect repair. We also confirm the accuracy of edge repair, Ga+ deep implantation effects and the environmental stability of FIB and blue laser repair tools. Finally, we measure the topography of the repaired photomask by AFM and AIMS.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"280 1","pages":"159-162"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77582906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820837
Dohyung Kim, S. Ha
In this paper, we focus on communication protocols which integrate control modules and function modules. Among others, asynchronous interaction enables the FSM model to control the scheduling of the dataflow model and to change the parameter in the data flow modules. Compared with previous approaches, the proposed technique supports formal specification for each component and provides protocols which integrate the two models in a flexible way.
{"title":"Asynchronous interaction between FSM and dataflow models","authors":"Dohyung Kim, S. Ha","doi":"10.1109/ICVC.1999.820837","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820837","url":null,"abstract":"In this paper, we focus on communication protocols which integrate control modules and function modules. Among others, asynchronous interaction enables the FSM model to control the scheduling of the dataflow model and to change the parameter in the data flow modules. Compared with previous approaches, the proposed technique supports formal specification for each component and provides protocols which integrate the two models in a flexible way.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"117 2 1","pages":"103-106"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85654211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820886
B. Lee, N. Park, S. Han, Kyungho Lee
We found that RTA of amorphous WN/sub x//poly-Si resulted in denudation of nitrogen atoms with the formation of low resistivity W and a highly reliable in situ barrier layer simultaneously. Furthermore, electrical characteristics of the denuded-WN/sub x//poly-Si gate were superior to those of W/WN/sub x//poly-Si gate after selective oxidation and post anneal processes.
{"title":"Denuded-WN/sub x//poly-Si gate technology for deep sub-micron CMOS","authors":"B. Lee, N. Park, S. Han, Kyungho Lee","doi":"10.1109/ICVC.1999.820886","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820886","url":null,"abstract":"We found that RTA of amorphous WN/sub x//poly-Si resulted in denudation of nitrogen atoms with the formation of low resistivity W and a highly reliable in situ barrier layer simultaneously. Furthermore, electrical characteristics of the denuded-WN/sub x//poly-Si gate were superior to those of W/WN/sub x//poly-Si gate after selective oxidation and post anneal processes.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"38 1","pages":"225-228"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79786363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820812
M. Sarrafzadeh, Maogang Wang
In this paper, we focus on the physical design problems and their interaction with higher- and lower-levels. We propose to study the interaction between various cost functions in placement. In particular, we will consider, net-cut, wire-length, congestion, and timing. We show that minimizing wire-length may (and in general, will) create locally congested regions. We demonstrate that most other congestion related objectives are ill behaved and they should only be used in a post processing step. Using a post processing stage is found to be more effective than optimizing the congestion in one step. For the relationship between wire-length and net-cut, we demonstrate that they are correlated differently in different hierarchical levels.
{"title":"Interaction among cost functions in placement","authors":"M. Sarrafzadeh, Maogang Wang","doi":"10.1109/ICVC.1999.820812","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820812","url":null,"abstract":"In this paper, we focus on the physical design problems and their interaction with higher- and lower-levels. We propose to study the interaction between various cost functions in placement. In particular, we will consider, net-cut, wire-length, congestion, and timing. We show that minimizing wire-length may (and in general, will) create locally congested regions. We demonstrate that most other congestion related objectives are ill behaved and they should only be used in a post processing step. Using a post processing stage is found to be more effective than optimizing the congestion in one step. For the relationship between wire-length and net-cut, we demonstrate that they are correlated differently in different hierarchical levels.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"1 1","pages":"32-36"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84068736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820879
Sang Jong Park, Kwangrak Kim, J. Kim, Seong Joon Lee, Sun-Woong Woo, J. Lee
As the refractive index of the passivation layer in a CMOS image sensor was increased and hence as the passivation layer became nitrided, the barrier property against contaminants was improved because of the densification of the layer. The result of the ray tracing simulation showed the improvement in cohesivity of light at the photodiode as well. However, the high refractive index of the passivation layer caused high reflection at the surface and hence a decrease in sensitivity. Moreover, with the use of ARL (Anti Reflection Layer) to control the high reflection at the Si substrate, the increase in the refractive index of ARL brought about the increase in sensitivity due to the low reflection at the Si substrate.
{"title":"Optical sensitivity and barrier property depending on ILD layers of CMOS image sensor device","authors":"Sang Jong Park, Kwangrak Kim, J. Kim, Seong Joon Lee, Sun-Woong Woo, J. Lee","doi":"10.1109/ICVC.1999.820879","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820879","url":null,"abstract":"As the refractive index of the passivation layer in a CMOS image sensor was increased and hence as the passivation layer became nitrided, the barrier property against contaminants was improved because of the densification of the layer. The result of the ray tracing simulation showed the improvement in cohesivity of light at the photodiode as well. However, the high refractive index of the passivation layer caused high reflection at the surface and hence a decrease in sensitivity. Moreover, with the use of ARL (Anti Reflection Layer) to control the high reflection at the Si substrate, the increase in the refractive index of ARL brought about the increase in sensitivity due to the low reflection at the Si substrate.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"152 1","pages":"211-213"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77879344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820815
M. Jang, H. Lee, Myoung-Kyu Park, Hae-Wang Lee, Kyung-Jin Yoo, Sang-Bok Lee, Sungwoong Chung, D. Kang, J. Hwang
In this paper the dependence of interconnect line-induced delay time on the repeater size is characterized. In case of capacitance dominant interconnect line, the total delay time decreases as repeater size increases. However there exists a point where the delay time becomes minimum when both of resistance and capacitance of interconnect line becomes larger than those of transistor. The optimum repeater size is obtained using an analytic equation and the experimental results showed good agreement with the calculation.
{"title":"Optimization of repeater size to minimize interconnect line-induced delay time for high performance VLSI circuits","authors":"M. Jang, H. Lee, Myoung-Kyu Park, Hae-Wang Lee, Kyung-Jin Yoo, Sang-Bok Lee, Sungwoong Chung, D. Kang, J. Hwang","doi":"10.1109/ICVC.1999.820815","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820815","url":null,"abstract":"In this paper the dependence of interconnect line-induced delay time on the repeater size is characterized. In case of capacitance dominant interconnect line, the total delay time decreases as repeater size increases. However there exists a point where the delay time becomes minimum when both of resistance and capacitance of interconnect line becomes larger than those of transistor. The optimum repeater size is obtained using an analytic equation and the experimental results showed good agreement with the calculation.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"42 1","pages":"41-44"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90265773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820851
Hyun-Sik Kim, Jong-Hyon Ahn, Duk-Min Lee, Soo-Cheol Lee, K. Suh
In deep sub-quarter micron, Transient Enhanced Diffusion (TED) of gate channel (Lgate) region seriously gives rise to the variation of device characteristics due to the increase of interstitial silicon atoms. Channel impurity variation by this TED becomes more dominant factor to bring about the severe fluctuation of threshold voltage than the gate length or the gate oxide thickness variation does. This work presents the results of suppressing Reverse Short Channel Effect (RSCE) which severely is showed in the selectively implanted channel process using local implant process. In case of using boron as the n-channel dopant, the 10% improvement of RSCE and the 35% reduction of Vth fluctuation are achieved through TED suppression by Rapid Thermal Anneal (RTA) treatment. We not only demonstrated the 15% increase of current drive but also removed RSCE clearly by realizing of Super-Steep Retrograded (SSR) channel doping profile with indium.
{"title":"High performance 0.18 um nMOSFET by TED suppression","authors":"Hyun-Sik Kim, Jong-Hyon Ahn, Duk-Min Lee, Soo-Cheol Lee, K. Suh","doi":"10.1109/ICVC.1999.820851","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820851","url":null,"abstract":"In deep sub-quarter micron, Transient Enhanced Diffusion (TED) of gate channel (Lgate) region seriously gives rise to the variation of device characteristics due to the increase of interstitial silicon atoms. Channel impurity variation by this TED becomes more dominant factor to bring about the severe fluctuation of threshold voltage than the gate length or the gate oxide thickness variation does. This work presents the results of suppressing Reverse Short Channel Effect (RSCE) which severely is showed in the selectively implanted channel process using local implant process. In case of using boron as the n-channel dopant, the 10% improvement of RSCE and the 35% reduction of Vth fluctuation are achieved through TED suppression by Rapid Thermal Anneal (RTA) treatment. We not only demonstrated the 15% increase of current drive but also removed RSCE clearly by realizing of Super-Steep Retrograded (SSR) channel doping profile with indium.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"120 1","pages":"140-142"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80633674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：