M. Sekine, S. Ueda, M. Kogure, T. Takei, Masami Aihara, E. Yano, K. Iwawaki, K. Yamagishi, K. Kohno, T. Kitahara, T. Fukasawa
A VLSI CAD (computer-aided design) system has been enhanced by adding several tools. It consists of a mixed-level simulator, logic synthesis, layout systems, a functional test generation assistance, etc. The functional simulator, which is on a laptop PC, is for a 50 K-gate class LSI, and the mixed level simulator, which is on an EWS and a mainframe, is for above-100 K-gate VLSI. In-house designer groups have reported that the design time is cut in half using the system. A functional schematic capture provides a more friendly user interface than a logic schematic capture. A novel approach to functional test generation is also provided
{"title":"An advanced design system: design capture, functional test generation, mixed level simulation and logic synthesis [VLSI]","authors":"M. Sekine, S. Ueda, M. Kogure, T. Takei, Masami Aihara, E. Yano, K. Iwawaki, K. Yamagishi, K. Kohno, T. Kitahara, T. Fukasawa","doi":"10.1109/CICC.1989.56789","DOIUrl":"https://doi.org/10.1109/CICC.1989.56789","url":null,"abstract":"A VLSI CAD (computer-aided design) system has been enhanced by adding several tools. It consists of a mixed-level simulator, logic synthesis, layout systems, a functional test generation assistance, etc. The functional simulator, which is on a laptop PC, is for a 50 K-gate class LSI, and the mixed level simulator, which is on an EWS and a mainframe, is for above-100 K-gate VLSI. In-house designer groups have reported that the design time is cut in half using the system. A functional schematic capture provides a more friendly user interface than a logic schematic capture. A novel approach to functional test generation is also provided","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116033083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Cox, David Leroy Guertin, C. Johnson, B. G. Rudolph, R. R. Williams, R. Piro, D. Stout
A major problem in VLSI system design is controlling off-chip driver characteristics and skew in clock generation as process parameters, temperature, and supply voltage vary. A control circuit methodology has been developed that senses the relative performance of a CMOS chip and transmits a digitally encoded state to off-chip driver and clock generation circuits to control their operating characteristics
{"title":"VLSI performance compensation for off-chip drivers and clock generation","authors":"D. Cox, David Leroy Guertin, C. Johnson, B. G. Rudolph, R. R. Williams, R. Piro, D. Stout","doi":"10.1109/CICC.1989.56752","DOIUrl":"https://doi.org/10.1109/CICC.1989.56752","url":null,"abstract":"A major problem in VLSI system design is controlling off-chip driver characteristics and skew in clock generation as process parameters, temperature, and supply voltage vary. A control circuit methodology has been developed that senses the relative performance of a CMOS chip and transmits a digitally encoded state to off-chip driver and clock generation circuits to control their operating characteristics","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114802242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The input/output specifictions (IOSpec) analyzer is a tool designed to ensure that the original specifications of the IC design will be taken into account during verification and analysis. Design specifications tend to get distorted in the numerous intermediate steps that are associated with any design verification and analysis process, and therefore this task is essential for any design process. The IOSpec analyzer greatly reduces design verification and analysis turnaround time by automating an otherwise cumbersome and error-prone process. It can be used either as a stand-alone program or as a facility within an integrated design automation system. It uses an object-oriented, rule-based programming paradigm in conjunction with a customizable user interface. Although current applications are geared toward IC designs, the program can easily be extended for circuit board designs. The authors present the overall program architecture and its applications
{"title":"The input/output specifications analyzer for IC designs","authors":"E. S. Lee, H. Chang, K. W. Wu, R. Kovesdi","doi":"10.1109/CICC.1989.56787","DOIUrl":"https://doi.org/10.1109/CICC.1989.56787","url":null,"abstract":"The input/output specifictions (IOSpec) analyzer is a tool designed to ensure that the original specifications of the IC design will be taken into account during verification and analysis. Design specifications tend to get distorted in the numerous intermediate steps that are associated with any design verification and analysis process, and therefore this task is essential for any design process. The IOSpec analyzer greatly reduces design verification and analysis turnaround time by automating an otherwise cumbersome and error-prone process. It can be used either as a stand-alone program or as a facility within an integrated design automation system. It uses an object-oriented, rule-based programming paradigm in conjunction with a customizable user interface. Although current applications are geared toward IC designs, the program can easily be extended for circuit board designs. The authors present the overall program architecture and its applications","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134125859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Yotsuyanagi, A. Yukawa, K. Hino-oka, K. Shiraki, H. Abiko
A 12-bit 5-μs CMOS analog-to-digital converter (ADC) has been realized in a 4-mm2 area with power consumption of only 25 mW ADC with 25 mW at a supply voltage of 5 V. Trimming and software calibration were not used. A four-step recursive subranging architecture has been adopted
{"title":"A 12 bit 5 μsec CMOS recursive ADC with 25 mW power consumption","authors":"M. Yotsuyanagi, A. Yukawa, K. Hino-oka, K. Shiraki, H. Abiko","doi":"10.1109/CICC.1989.56713","DOIUrl":"https://doi.org/10.1109/CICC.1989.56713","url":null,"abstract":"A 12-bit 5-μs CMOS analog-to-digital converter (ADC) has been realized in a 4-mm2 area with power consumption of only 25 mW ADC with 25 mW at a supply voltage of 5 V. Trimming and software calibration were not used. A four-step recursive subranging architecture has been adopted","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133313053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Tamamura, S. Emori, Yoshio Watanabe, Isao Shimotsuhama, N. Kikuchi, W. Ishibashi, K. Tachibana
The authors present a novel semicustom IC called the gate masterslice, which enables a clear eye pattern to be obtained for high-bit-rate signals. Key design features of the gate masterslice are: an advanced Si bipolar process, chip structure that reduces signal interference rather than increasing gate density, and internal connection using only the second metal layer
{"title":"4 Gb/s ECL gate masterslice","authors":"M. Tamamura, S. Emori, Yoshio Watanabe, Isao Shimotsuhama, N. Kikuchi, W. Ishibashi, K. Tachibana","doi":"10.1109/CICC.1989.56757","DOIUrl":"https://doi.org/10.1109/CICC.1989.56757","url":null,"abstract":"The authors present a novel semicustom IC called the gate masterslice, which enables a clear eye pattern to be obtained for high-bit-rate signals. Key design features of the gate masterslice are: an advanced Si bipolar process, chip structure that reduces signal interference rather than increasing gate density, and internal connection using only the second metal layer","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123873949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Shigeya Tanaka, T. Hotta, M. Iwamura, T. Yamauchi, T. Bandoh, A. Hotta, T. Nakano, S. Iwamoto, S. Adachi
A BiCMOS 32-bit execution has been developed to attain 70-MHz (typical) speed using 1.0-μm BiCMOS technology. The three important components are: (1) an arithmetic unit, which uses a 0.6-ns 8-bit carry propagation circuit; (2) a 2.5-ns 54-W×32-b four-port register file, which uses a BiCMOS sense circuit and dynamic bus drivers; and (3) a flag generator, which uses a novel all-bit-zero generation algorithm and generates in parallel with the arithmetic computation. A CLSI computer has been implemented with the above components, and 70-MHz register-register operation has been achieved
{"title":"A BiCMOS 32-bit execution unit for 70 MHz VLSI computer","authors":"Shigeya Tanaka, T. Hotta, M. Iwamura, T. Yamauchi, T. Bandoh, A. Hotta, T. Nakano, S. Iwamoto, S. Adachi","doi":"10.1109/CICC.1989.56730","DOIUrl":"https://doi.org/10.1109/CICC.1989.56730","url":null,"abstract":"A BiCMOS 32-bit execution has been developed to attain 70-MHz (typical) speed using 1.0-μm BiCMOS technology. The three important components are: (1) an arithmetic unit, which uses a 0.6-ns 8-bit carry propagation circuit; (2) a 2.5-ns 54-W×32-b four-port register file, which uses a BiCMOS sense circuit and dynamic bus drivers; and (3) a flag generator, which uses a novel all-bit-zero generation algorithm and generates in parallel with the arithmetic computation. A CLSI computer has been implemented with the above components, and 70-MHz register-register operation has been achieved","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125196436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Yano, T. Yamanaka, T. Nishida, M. Saitoh, K. Shimohigashi, A. Shimizu
A 3.8-ns, 257-mW CMOS 16×16 multiplier with a supply voltage of 4 V is described. A complementary pass transistor logic (CPL) is proposed and applied to almost the entire critical path. The CPL consists of complementary input/output, an NMOS-pass-transistor logic network, and CMOS output inverters. The CPL is twice as fast as the conventional CMOS due to lower input capacitance and greater logic construction ability. Its multiplication time is believed to be the fastest ever reported, even including times of bipolar and GaAs ICs, and it is shown to be further enhanced to 2.6 ns and 60 mW at 77 K
{"title":"A 3.8 ns CMOS 16×16 multiplier using complementary pass transistor logic","authors":"K. Yano, T. Yamanaka, T. Nishida, M. Saitoh, K. Shimohigashi, A. Shimizu","doi":"10.1109/CICC.1989.56843","DOIUrl":"https://doi.org/10.1109/CICC.1989.56843","url":null,"abstract":"A 3.8-ns, 257-mW CMOS 16×16 multiplier with a supply voltage of 4 V is described. A complementary pass transistor logic (CPL) is proposed and applied to almost the entire critical path. The CPL consists of complementary input/output, an NMOS-pass-transistor logic network, and CMOS output inverters. The CPL is twice as fast as the conventional CMOS due to lower input capacitance and greater logic construction ability. Its multiplication time is believed to be the fastest ever reported, even including times of bipolar and GaAs ICs, and it is shown to be further enhanced to 2.6 ns and 60 mW at 77 K","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"147 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127728416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A.J.-H. Lee, J. A. Sabnis, M. Saniski, G. P. Sampson
The authors describe a very-high-performance CMOS device designed to transmit and receive packetized data. During the transmitting operations, bytewide data are converted to a single serial bit stream that can be transmitted on an optical fiber. In the receiving operations, the serial bit stream is converted into byte format with appropriate frame detection. Operations with bit rate at 400 Mb/s have been demonstrated. The on-chip pseudo-ECL input and output buffers provide high-speed, low-power interfaces
{"title":"A 400 MHz CMOS packet transmitter-receiver chip","authors":"A.J.-H. Lee, J. A. Sabnis, M. Saniski, G. P. Sampson","doi":"10.1109/CICC.1989.56772","DOIUrl":"https://doi.org/10.1109/CICC.1989.56772","url":null,"abstract":"The authors describe a very-high-performance CMOS device designed to transmit and receive packetized data. During the transmitting operations, bytewide data are converted to a single serial bit stream that can be transmitted on an optical fiber. In the receiving operations, the serial bit stream is converted into byte format with appropriate frame detection. Operations with bit rate at 400 Mb/s have been demonstrated. The on-chip pseudo-ECL input and output buffers provide high-speed, low-power interfaces","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129854581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A CMOS ALU (arithmetic logic unit) chip containing built-in current (BIC) sensors, which perform self-testing of the ALU, is described. The performance of two ALUs (one with and one without a BIC sensor) is analyzed by using externally applied test vectors and linear feedback shift register for BIC and for stuck-fault testing. The results demonstrate that the BIC testing methodology is well suited for initial die testing of CMOS ICs as well as for concurrent self-testing of highly reliable systems
{"title":"A self-testing ALU using built-in current sensing","authors":"P. Nigh, Wojciech Maly","doi":"10.1109/CICC.1989.56807","DOIUrl":"https://doi.org/10.1109/CICC.1989.56807","url":null,"abstract":"A CMOS ALU (arithmetic logic unit) chip containing built-in current (BIC) sensors, which perform self-testing of the ALU, is described. The performance of two ALUs (one with and one without a BIC sensor) is analyzed by using externally applied test vectors and linear feedback shift register for BIC and for stuck-fault testing. The results demonstrate that the BIC testing methodology is well suited for initial die testing of CMOS ICs as well as for concurrent self-testing of highly reliable systems","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127901451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Koichi Tanaka, K. Fujimoto, E. Katsumata, T. Yaguchi, K. Tamaru, A. Kanuma, S. Iida, A. Nishikawa, H. Shiraishi, T. Mineoka, T. Shimamura
A description is given of the architecture of the token-ring LAN controller (TRC) compatible with IEEE 802.5 media access control (MAC) protocol, which integrates a frame transmit/receive hardware, a high-speed protocol processor, a three-channel DMA controller (DMAC) and large-capacity dual-port RAMs. The performance analysis of the frame transmit/receive shows that the TRC is suitable not only for small computers, but also for high-performance applications
{"title":"VLSI architecture for IEEE 802.5 token-ring LAN controller","authors":"Koichi Tanaka, K. Fujimoto, E. Katsumata, T. Yaguchi, K. Tamaru, A. Kanuma, S. Iida, A. Nishikawa, H. Shiraishi, T. Mineoka, T. Shimamura","doi":"10.1109/CICC.1989.56759","DOIUrl":"https://doi.org/10.1109/CICC.1989.56759","url":null,"abstract":"A description is given of the architecture of the token-ring LAN controller (TRC) compatible with IEEE 802.5 media access control (MAC) protocol, which integrates a frame transmit/receive hardware, a high-speed protocol processor, a three-channel DMA controller (DMAC) and large-capacity dual-port RAMs. The performance analysis of the frame transmit/receive shows that the TRC is suitable not only for small computers, but also for high-performance applications","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"36 11","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120921440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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